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https://github.com/c64scene-ar/llvm-6502.git
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Add __builtin_setjmp/_longjmp supprt in X86 backend
- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
790047620a
commit
6c0e04c823
@ -1302,7 +1302,9 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
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// that are not a MemSDNode, and thus don't have proper addrspace info.
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Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
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Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
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Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
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Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
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Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
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Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
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unsigned AddrSpace =
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cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
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// AddrSpace 256 -> GS, 257 -> FS.
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@ -457,6 +457,14 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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}
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setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
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// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
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// SjLj exception handling but a light-weight setjmp/longjmp replacement to
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// support continuation, user-level threading, and etc.. As a result, not
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// other SjLj exception interfaces are implemented and please don't build
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// your own exception handling based on them.
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// LLVM/Clang supports zero-cost DWARF exception handling.
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setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
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setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
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// Darwin ABI issue.
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setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
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@ -10351,6 +10359,21 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
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Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
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}
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SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
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DAG.getVTList(MVT::i32, MVT::Other),
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Op.getOperand(0), Op.getOperand(1));
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}
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SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
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Op.getOperand(0), Op.getOperand(1));
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}
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static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
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return Op.getOperand(0);
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}
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@ -11375,6 +11398,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
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case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
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case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
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case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
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case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
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case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
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@ -11667,6 +11692,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
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case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
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case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
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case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
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case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
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case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
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case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
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case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
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@ -13212,6 +13239,173 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
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return BB;
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}
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MachineBasicBlock *
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X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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DebugLoc DL = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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MachineFunction *MF = MBB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const BasicBlock *BB = MBB->getBasicBlock();
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MachineFunction::iterator I = MBB;
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++I;
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// Memory Reference
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MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
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MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
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unsigned DstReg;
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unsigned MemOpndSlot = 0;
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unsigned CurOp = 0;
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DstReg = MI->getOperand(CurOp++).getReg();
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const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
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assert(RC->hasType(MVT::i32) && "Invalid destination!");
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unsigned mainDstReg = MRI.createVirtualRegister(RC);
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unsigned restoreDstReg = MRI.createVirtualRegister(RC);
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MemOpndSlot = CurOp;
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MVT PVT = getPointerTy();
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assert((PVT == MVT::i64 || PVT == MVT::i32) &&
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"Invalid Pointer Size!");
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// For v = setjmp(buf), we generate
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//
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// thisMBB:
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// buf[Label_Offset] = ljMBB
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// SjLjSetup restoreMBB
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//
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// mainMBB:
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// v_main = 0
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//
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// sinkMBB:
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// v = phi(main, restore)
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//
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// restoreMBB:
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// v_restore = 1
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MachineBasicBlock *thisMBB = MBB;
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MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
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MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
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MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
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MF->insert(I, mainMBB);
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MF->insert(I, sinkMBB);
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MF->push_back(restoreMBB);
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MachineInstrBuilder MIB;
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), MBB,
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llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
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// thisMBB:
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unsigned PtrImmStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
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const int64_t Label_Offset = 1 * PVT.getStoreSize();
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// Store IP
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MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrImmStoreOpc));
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for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
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if (i == X86::AddrDisp)
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MIB.addDisp(MI->getOperand(MemOpndSlot + i), Label_Offset);
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else
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MIB.addOperand(MI->getOperand(MemOpndSlot + i));
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}
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MIB.addMBB(restoreMBB);
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MIB.setMemRefs(MMOBegin, MMOEnd);
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// Setup
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MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
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.addMBB(restoreMBB);
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MIB.addRegMask(RegInfo->getNoPreservedMask());
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thisMBB->addSuccessor(mainMBB);
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thisMBB->addSuccessor(restoreMBB);
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// mainMBB:
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// EAX = 0
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BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
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mainMBB->addSuccessor(sinkMBB);
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// sinkMBB:
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BuildMI(*sinkMBB, sinkMBB->begin(), DL,
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TII->get(X86::PHI), DstReg)
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.addReg(mainDstReg).addMBB(mainMBB)
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.addReg(restoreDstReg).addMBB(restoreMBB);
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// restoreMBB:
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BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
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BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
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restoreMBB->addSuccessor(sinkMBB);
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MI->eraseFromParent();
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return sinkMBB;
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}
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MachineBasicBlock *
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X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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DebugLoc DL = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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MachineFunction *MF = MBB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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// Memory Reference
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MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
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MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
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MVT PVT = getPointerTy();
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assert((PVT == MVT::i64 || PVT == MVT::i32) &&
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"Invalid Pointer Size!");
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const TargetRegisterClass *RC =
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(PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
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unsigned Tmp = MRI.createVirtualRegister(RC);
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// Since FP is only updated here but NOT referenced, it's treated as GPR.
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unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
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unsigned SP = RegInfo->getStackRegister();
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MachineInstrBuilder MIB;
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const int64_t Label_Offset = 1 * PVT.getStoreSize();
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const int64_t SP_Offset = 2 * PVT.getStoreSize();
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unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
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unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
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// Reload FP
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MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
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for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
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MIB.addOperand(MI->getOperand(i));
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MIB.setMemRefs(MMOBegin, MMOEnd);
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// Reload IP
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MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
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for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
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if (i == X86::AddrDisp)
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MIB.addDisp(MI->getOperand(i), Label_Offset);
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else
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MIB.addOperand(MI->getOperand(i));
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}
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MIB.setMemRefs(MMOBegin, MMOEnd);
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// Reload SP
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MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
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for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
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if (i == X86::AddrDisp)
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MIB.addDisp(MI->getOperand(i), SP_Offset);
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else
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MIB.addOperand(MI->getOperand(i));
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}
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MIB.setMemRefs(MMOBegin, MMOEnd);
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// Jump
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BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
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MI->eraseFromParent();
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return MBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -13427,6 +13621,14 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::VAARG_64:
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return EmitVAARG64WithCustomInserter(MI, BB);
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case X86::EH_SjLj_SetJmp32:
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case X86::EH_SjLj_SetJmp64:
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return emitEHSjLjSetJmp(MI, BB);
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case X86::EH_SjLj_LongJmp32:
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case X86::EH_SjLj_LongJmp64:
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return emitEHSjLjLongJmp(MI, BB);
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}
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}
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@ -217,6 +217,12 @@ namespace llvm {
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// EH_RETURN - Exception Handling helpers.
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EH_RETURN,
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// EH_SJLJ_SETJMP - SjLj exception handling setjmp.
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EH_SJLJ_SETJMP,
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// EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
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EH_SJLJ_LONGJMP,
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/// TC_RETURN - Tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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@ -810,6 +816,8 @@ namespace llvm {
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
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@ -906,6 +914,12 @@ namespace llvm {
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MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Emit nodes that will be selected as "test Op0,Op0", or something
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
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@ -165,6 +165,33 @@ def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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}
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let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
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usesCustomInserter = 1 in {
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def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
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"#EH_SJLJ_SETJMP32",
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[(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
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Requires<[In32BitMode]>;
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def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
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"#EH_SJLJ_SETJMP64",
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[(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
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Requires<[In64BitMode]>;
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let isTerminator = 1 in {
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def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
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"#EH_SJLJ_LONGJMP32",
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[(X86eh_sjlj_longjmp addr:$buf)]>,
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Requires<[In32BitMode]>;
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def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
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"#EH_SJLJ_LONGJMP64",
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[(X86eh_sjlj_longjmp addr:$buf)]>,
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Requires<[In64BitMode]>;
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}
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}
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let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
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def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
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"#EH_SjLj_Setup\t$dst", []>;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions used by segmented stacks.
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//
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@ -216,6 +216,14 @@ def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
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def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
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[SDNPHasChain]>;
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def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
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SDTypeProfile<1, 1, [SDTCisInt<0>,
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SDTCisPtrTy<1>]>,
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[SDNPHasChain, SDNPSideEffect]>;
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def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
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SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
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[SDNPHasChain, SDNPSideEffect]>;
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def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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@ -261,6 +261,11 @@ X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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return CSR_64_RegMask;
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}
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const uint32_t*
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X86RegisterInfo::getNoPreservedMask() const {
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return CSR_NoRegs_RegMask;
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}
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BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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@ -100,6 +100,7 @@ public:
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/// callee-save registers on this target.
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const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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const uint32_t *getNoPreservedMask() const;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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46
test/CodeGen/X86/sjlj.ll
Normal file
46
test/CodeGen/X86/sjlj.ll
Normal file
@ -0,0 +1,46 @@
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; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 -relocation-model=static | FileCheck --check-prefix=X86 %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7 | FileCheck --check-prefix=X64 %s
|
||||
|
||||
@buf = internal global [5 x i8*] zeroinitializer
|
||||
|
||||
declare i8* @llvm.frameaddress(i32) nounwind readnone
|
||||
|
||||
declare i8* @llvm.stacksave() nounwind
|
||||
|
||||
declare i32 @llvm.eh.sjlj.setjmp(i8*) nounwind
|
||||
|
||||
declare void @llvm.eh.sjlj.longjmp(i8*) nounwind
|
||||
|
||||
define i32 @sj0() nounwind {
|
||||
%fp = tail call i8* @llvm.frameaddress(i32 0)
|
||||
store i8* %fp, i8** getelementptr inbounds ([5 x i8*]* @buf, i64 0, i64 0), align 16
|
||||
%sp = tail call i8* @llvm.stacksave()
|
||||
store i8* %sp, i8** getelementptr inbounds ([5 x i8*]* @buf, i64 0, i64 2), align 16
|
||||
%r = tail call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([5 x i8*]* @buf to i8*))
|
||||
ret i32 %r
|
||||
; X86: sj0
|
||||
; x86: movl %ebp, buf
|
||||
; x86: movl ${{.*LBB.*}}, buf+4
|
||||
; X86: movl %esp, buf+8
|
||||
; X86: ret
|
||||
; X64: sj0
|
||||
; x64: movq %rbp, buf(%rip)
|
||||
; x64: movq ${{.*LBB.*}}, buf+8(%rip)
|
||||
; X64: movq %rsp, buf+16(%rip)
|
||||
; X64: ret
|
||||
}
|
||||
|
||||
define void @lj0() nounwind {
|
||||
tail call void @llvm.eh.sjlj.longjmp(i8* bitcast ([5 x i8*]* @buf to i8*))
|
||||
unreachable
|
||||
; X86: lj0
|
||||
; X86: movl buf, %ebp
|
||||
; X86: movl buf+4, %[[REG32:.*]]
|
||||
; X86: movl buf+8, %esp
|
||||
; X86: jmpl *%[[REG32]]
|
||||
; X64: lj0
|
||||
; X64: movq buf(%rip), %rbp
|
||||
; X64: movq buf+8(%rip), %[[REG64:.*]]
|
||||
; X64: movq buf+16(%rip), %rsp
|
||||
; X64: jmpq *%[[REG64]]
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user