mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Add the framework for a dag-dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24769 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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433dbdaa63
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@ -13,7 +13,8 @@ TARGET = SparcV8
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc
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SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
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SparcV8GenDAGISel.inc
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include $(LEVEL)/Makefile.common
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@ -23,6 +23,8 @@ namespace llvm {
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class TargetMachine;
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FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
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FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
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FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
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TargetMachine &TM);
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FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
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172
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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172
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -0,0 +1,172 @@
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//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the V8 target
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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};
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}
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SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
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addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
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computeRegisterProperties();
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}
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std::vector<SDOperand>
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SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand, SDOperand>
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SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand,SDOperand>
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SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand, SDOperand>
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SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SparcV8DAGToDAGISel : public SelectionDAGISel {
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SparcV8TargetLowering V8Lowering;
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public:
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SparcV8DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
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SDOperand Select(SDOperand Op);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcV8GenDAGISel.inc"
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};
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} // end anonymous namespace
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(Select(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
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N->getOpcode() < V8ISD::FIRST_NUMBER*/)
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return Op; // Already selected.
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// If this has already been converted, use it.
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std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
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if (CGMI != CodeGenMap.end()) return CGMI->second;
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switch (N->getOpcode()) {
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default: break;
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}
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return SelectCode(Op);
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}
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/// createPPCISelDag - This pass converts a legalized DAG into a
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/// PowerPC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
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return new SparcV8DAGToDAGISel(TM);
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}
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@ -20,12 +20,17 @@
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
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cl::opt<bool> DisableV8DAGDAG("disable-v8-dag-isel", cl::Hidden,
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cl::desc("Disable DAG-to-DAG isel for V8"),
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cl::init(1));
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}
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/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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@ -87,7 +92,10 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
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if (PrintMachineCode)
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PM.add(new PrintFunctionPass());
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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if (DisableV8DAGDAG)
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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else
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PM.add(createSparcV8ISelDag(*this));
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// Print machine instructions as they were initially generated.
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if (PrintMachineCode)
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@ -13,7 +13,8 @@ TARGET = SparcV8
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc
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SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
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SparcV8GenDAGISel.inc
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include $(LEVEL)/Makefile.common
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@ -23,6 +23,8 @@ namespace llvm {
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class TargetMachine;
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FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
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FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
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FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
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TargetMachine &TM);
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FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
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172
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
Normal file
172
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
Normal file
@ -0,0 +1,172 @@
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//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the V8 target
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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};
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}
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SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
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addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
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computeRegisterProperties();
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}
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std::vector<SDOperand>
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SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand, SDOperand>
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SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand,SDOperand>
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SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand, SDOperand>
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SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SparcV8DAGToDAGISel : public SelectionDAGISel {
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SparcV8TargetLowering V8Lowering;
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public:
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SparcV8DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
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SDOperand Select(SDOperand Op);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcV8GenDAGISel.inc"
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};
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} // end anonymous namespace
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(Select(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
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N->getOpcode() < V8ISD::FIRST_NUMBER*/)
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return Op; // Already selected.
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// If this has already been converted, use it.
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std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
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if (CGMI != CodeGenMap.end()) return CGMI->second;
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switch (N->getOpcode()) {
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default: break;
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}
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return SelectCode(Op);
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}
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/// createPPCISelDag - This pass converts a legalized DAG into a
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/// PowerPC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
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return new SparcV8DAGToDAGISel(TM);
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}
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@ -20,12 +20,17 @@
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
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cl::opt<bool> DisableV8DAGDAG("disable-v8-dag-isel", cl::Hidden,
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cl::desc("Disable DAG-to-DAG isel for V8"),
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cl::init(1));
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}
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/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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@ -87,7 +92,10 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
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if (PrintMachineCode)
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PM.add(new PrintFunctionPass());
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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if (DisableV8DAGDAG)
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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else
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PM.add(createSparcV8ISelDag(*this));
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|
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// Print machine instructions as they were initially generated.
|
||||
if (PrintMachineCode)
|
||||
|
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Reference in New Issue
Block a user