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ARM: Clean up copyPhysReg() a bit.

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No functional change, just cleaning things up for readability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193138 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2013-10-22 02:29:35 +00:00
parent 11d78777d5
commit 6c28682963
1 changed files with 47 additions and 27 deletions
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62
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@@ -690,26 +690,47 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
int Spacing = 1;
// Use VORRq when possible.
if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VORRq;
BeginIdx = ARM::qsub_0;
SubRegs = 2;
} else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VORRq;
BeginIdx = ARM::qsub_0;
SubRegs = 4;
// Fall back to VMOVD.
else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg))
Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
} else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VMOVD;
BeginIdx = ARM::dsub_0;
SubRegs = 2;
} else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VMOVD;
BeginIdx = ARM::dsub_0;
SubRegs = 3;
} else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VMOVD;
BeginIdx = ARM::dsub_0;
SubRegs = 4;
} else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::MOVr;
BeginIdx = ARM::gsub_0;
SubRegs = 2;
} else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VMOVD;
BeginIdx = ARM::dsub_0;
SubRegs = 2;
Spacing = 2;
} else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VMOVD;
BeginIdx = ARM::dsub_0;
SubRegs = 3;
Spacing = 2;
} else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
Opc = ARM::VMOVD;
BeginIdx = ARM::dsub_0;
SubRegs = 4;
Spacing = 2;
}
assert(Opc && "Impossible reg-to-reg copy");
@@ -732,8 +753,7 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
assert(!DstRegs.count(Src) && "destructive vector copy");
DstRegs.insert(Dst);
#endif
Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
.addReg(Src);
Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
// VORR takes two source operands.
if (Opc == ARM::VORRq)
Mov.addReg(Src);