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This patch fixes failures in the SingleSource/Regression/C/uint64_to_float
test case on PowerPC caused by rounding errors when converting from a 64-bit integer to a single-precision floating point. The reason for this are double-rounding effects, since on PowerPC we have to convert to an intermediate double-precision value first, which gets rounded to the final single-precision result. The patch fixes the problem by preparing the 64-bit integer so that the first conversion step to double-precision will always be exact, and the final rounding step will result in the correctly-rounded single-precision result. The generated code sequence is equivalent to what GCC would generate. When -enable-unsafe-fp-math is in effect, that extra effort is omitted and we accept possible rounding errors (just like GCC does as well). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166178 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4224,7 +4224,52 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
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return SDValue();
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if (Op.getOperand(0).getValueType() == MVT::i64) {
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SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
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SDValue SINT = Op.getOperand(0);
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// When converting to single-precision, we actually need to convert
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// to double-precision first and then round to single-precision.
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// To avoid double-rounding effects during that operation, we have
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// to prepare the input operand. Bits that might be truncated when
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// converting to double-precision are replaced by a bit that won't
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// be lost at this stage, but is below the single-precision rounding
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// position.
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//
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// However, if -enable-unsafe-fp-math is in effect, accept double
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// rounding to avoid the extra overhead.
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if (Op.getValueType() == MVT::f32 &&
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!DAG.getTarget().Options.UnsafeFPMath) {
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// Twiddle input to make sure the low 11 bits are zero. (If this
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// is the case, we are guaranteed the value will fit into the 53 bit
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// mantissa of an IEEE double-precision value without rounding.)
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// If any of those low 11 bits were not zero originally, make sure
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// bit 12 (value 2048) is set instead, so that the final rounding
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// to single-precision gets the correct result.
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SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
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SINT, DAG.getConstant(2047, MVT::i64));
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Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
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Round, DAG.getConstant(2047, MVT::i64));
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Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
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Round = DAG.getNode(ISD::AND, dl, MVT::i64,
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Round, DAG.getConstant(-2048, MVT::i64));
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// However, we cannot use that value unconditionally: if the magnitude
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// of the input value is small, the bit-twiddling we did above might
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// end up visibly changing the output. Fortunately, in that case, we
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// don't need to twiddle bits since the original input will convert
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// exactly to double-precision floating-point already. Therefore,
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// construct a conditional to use the original value if the top 11
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// bits are all sign-bit copies, and use the rounded value computed
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// above otherwise.
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SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
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SINT, DAG.getConstant(53, MVT::i32));
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Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
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Cond, DAG.getConstant(1, MVT::i64));
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Cond = DAG.getSetCC(dl, MVT::i32,
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Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
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SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
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}
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SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
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SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
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if (Op.getValueType() == MVT::f32)
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FP = DAG.getNode(ISD::FP_ROUND, dl,
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27
test/CodeGen/PowerPC/i64_fp_round.ll
Normal file
27
test/CodeGen/PowerPC/i64_fp_round.ll
Normal file
@ -0,0 +1,27 @@
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; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @test(i64 %x) nounwind readnone {
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entry:
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%conv = sitofp i64 %x to float
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ret float %conv
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}
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; Verify that we get the code sequence needed to avoid double-rounding.
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; Note that only parts of the sequence are checked for here, to allow
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; for minor code generation differences.
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; CHECK: sradi [[REGISTER:[0-9]+]], 3, 53
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; CHECK: addi [[REGISTER:[0-9]+]], [[REGISTER]], 1
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; CHECK: cmpldi 0, [[REGISTER]], 1
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; CHECK: isel [[REGISTER:[0-9]+]], {{[0-9]+}}, 3, 1
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; CHECK: std [[REGISTER]], -{{[0-9]+}}(1)
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; Also check that with -enable-unsafe-fp-math we do not get that extra
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; code sequence. Simply verify that there is no "isel" present.
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; RUN: llc -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE
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; CHECK-UNSAFE-NOT: isel
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