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[X86][AVX] Fix failure due to a missing ISel pattern to select VBROADCAST nodes (PR23259).
This fixes a regression introduced at revision 218263. On AVX, if we optimize for size, a splat build_vector of a load is lowered into a VBROADCAST node. This is done even if the value type of the splat build_vector node is v2i64. Since AVX doesn't support v2f64/v2i64 broadcasts, revision 218263 added two extra tablegen patterns to allow selecting a VMOVDDUPrm from an X86VBroadcast where the scalar element comes from a loadi64/loadf64. However, revision 218263 forgot to add an extra fallback pattern for the case where we have a X86VBroadcast of a loadi64 with multiple uses. This patch adds the missing tablegen pattern in X86InstrSSE.td. This patch also adds an extra test to 'splat-for-size.ll' to verify that ISel doesn't crash with a 'fatal error in the backend' due to a missing AVX pattern to select v2i64 X86ISD::BROADCAST nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235509 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5223,9 +5223,9 @@ let Predicates = [HasAVX] in {
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let Predicates = [UseAVX, OptForSize] in {
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def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
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(VMOVDDUPrm addr:$src)>;
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(VMOVDDUPrm addr:$src)>;
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def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
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(VMOVDDUPrm addr:$src)>;
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(VMOVDDUPrm addr:$src)>;
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}
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let Predicates = [UseSSE3] in {
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@ -8478,6 +8478,8 @@ let Predicates = [HasAVX] in {
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def : Pat<(v2f64 (X86VBroadcast f64:$src)),
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(VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
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def : Pat<(v2i64 (X86VBroadcast i64:$src)),
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(VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
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}
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//===----------------------------------------------------------------------===//
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@ -138,4 +138,18 @@ define <32 x i8> @splat_v32i8(<32 x i8> %x) #0 {
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; CHECK: retq
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}
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; PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
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; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
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; loadi16 with multiple uses.
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@A = common global <3 x i64> zeroinitializer, align 32
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define <8 x i64> @pr23259() #0 {
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entry:
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%0 = load <4 x i64>, <4 x i64>* bitcast (<3 x i64>* @A to <4 x i64>*), align 32
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%1 = shufflevector <4 x i64> %0, <4 x i64> undef, <3 x i32> <i32 undef, i32 undef, i32 2>
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%shuffle = shufflevector <3 x i64> <i64 1, i64 undef, i64 undef>, <3 x i64> %1, <8 x i32> <i32 5, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i64> %shuffle
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}
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attributes #0 = { optsize }
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