6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.

Browse Source 
rdar://problem/9184053


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-25 17:31:16 +00:00
parent 15a3ea0628
commit 6c3891067b
2 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2951,6 +2951,11 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
case ARM::WFI: case ARM::WFI:
case ARM::SEV: case ARM::SEV:
return true; return true;
case ARM::SWP:
case ARM::SWPB:
// SWP, SWPB: Rd Rm Rn
// Delegate to DisassembleLdStExFrm()....
return DisassembleLdStExFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
default: default:
break; break;
} }

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -184,3 +184,6 @@
# CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc} # CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x1d 0xe9 0x11 0x99 0x1d 0xe9
# CHECK: swpge r3, r2, [r6]
0x92 0x30 0x06 0xa1