6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-19 03:29:22 +00:00
Code Issues Projects Releases Wiki Activity

fix indentation

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-07 06:37:02 +00:00
parent 094c8fcd14
commit 6c4dad0b8b
1 changed files with 57 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -591,63 +591,63 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
// If we know the result of a setcc has the top bits zero, use this info.
switch (Op.getOpcode()) {
case ISD::Constant:
return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
case ISD::SETCC:
return ((Mask & 1) == 0) &&
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
case ISD::ZEXTLOAD:
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::ZERO_EXTEND:
SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
case ISD::AssertZext:
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
// FALL THROUGH
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
case ISD::SELECT:
return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
case ISD::SELECT_CC:
return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
case ISD::SRL:
// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t NewVal = Mask << ShAmt->getValue();
SrcBits = MVT::getSizeInBits(Op.getValueType());
if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
case ISD::SHL:
// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t NewVal = Mask >> ShAmt->getValue();
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
case ISD::CTTZ:
case ISD::CTLZ:
case ISD::CTPOP:
// Bit counting instructions can not set the high bits of the result
// register. The max number of bits sets depends on the input.
return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
// TODO we could handle some SRA cases here.
default: break;
case ISD::Constant:
return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
case ISD::SETCC:
return ((Mask & 1) == 0) &&
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
case ISD::ZEXTLOAD:
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::ZERO_EXTEND:
SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
case ISD::AssertZext:
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
// FALL THROUGH
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
case ISD::SELECT:
return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
case ISD::SELECT_CC:
return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
case ISD::SRL:
// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t NewVal = Mask << ShAmt->getValue();
SrcBits = MVT::getSizeInBits(Op.getValueType());
if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
case ISD::SHL:
// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t NewVal = Mask >> ShAmt->getValue();
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
case ISD::CTTZ:
case ISD::CTLZ:
case ISD::CTPOP:
// Bit counting instructions can not set the high bits of the result
// register. The max number of bits sets depends on the input.
return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
// TODO we could handle some SRA cases here.
default: break;
}
return false;