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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
Revert this temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -208,10 +208,8 @@ ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
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AddDefaultPred(MIB);
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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bool isKill = true;
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// Add the callee-saved register as live-in unless it's LR and
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@ -227,58 +225,15 @@ ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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if (isKill)
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MBB.addLiveIn(Reg);
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if (!isARMPushRegister(Reg)) {
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// Insert the spill to the stack frame. The register is killed at the spill
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//
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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storeRegToStackSlot(MBB, MI, Reg, isKill,
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CSI[i-1].getFrameIdx(), RC, TRI);
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} else
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MIB.addReg(Reg, getKillRegState(isKill));
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CSI[i].getFrameIdx(), RC, TRI);
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}
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return true;
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}
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bool
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ARMBaseInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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if (CSI.empty())
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return false;
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bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
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DebugLoc DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
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AddDefaultPred(MIB);
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bool NumRegs = false;
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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if (Reg == ARM::LR && !isVarArg) {
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Reg = ARM::PC;
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(*MIB).setDesc(get(ARM::tPOP_RET));
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MI = MBB.erase(MI);
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}
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if (!isARMPushRegister(Reg)) {
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i-1].getFrameIdx(), RC, TRI);
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} else
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MIB.addReg(Reg, getDefRegState(true));
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NumRegs = true;
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}
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// It's illegal to emit pop instruction without operands.
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if (NumRegs)
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MBB.insert(MI, &*MIB);
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else
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MF.DeleteMachineInstr(MIB);
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return true;
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}
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// Branch analysis.
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bool
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ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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@ -211,11 +211,6 @@ public:
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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@ -1667,9 +1667,9 @@ static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
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int Opc1, int Opc2, unsigned Area,
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const ARMSubtarget &STI) {
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while (MBBI != MBB.end() &&
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((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2))) {
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if (Area == 3) {
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((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
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MBBI->getOperand(1).isFI()) {
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if (Area != 0) {
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bool Done = false;
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unsigned Category = 0;
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switch (MBBI->getOperand(0).getReg()) {
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@ -1759,7 +1759,9 @@ emitPrologue(MachineFunction &MF) const {
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}
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}
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movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 1, STI);
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// Build the new SUBri to adjust SP for integer callee-save spill area 1.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
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// Set FP to point to the stack slot that contains the previous FP.
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// For Darwin, FP is R7, which has now been stored in spill area 1.
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@ -1779,7 +1781,7 @@ emitPrologue(MachineFunction &MF) const {
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
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// Build the new SUBri to adjust SP for FP callee-save spill area.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 2, STI);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
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// Determine starting offsets of spill areas.
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@ -1873,25 +1875,11 @@ static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
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static bool isCSRestore(MachineInstr *MI,
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const ARMBaseInstrInfo &TII,
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const unsigned *CSRegs) {
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// Integer spill area is handled with pop.
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if (MI->getOpcode() == ARM::tRestore ||
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MI->getOpcode() == ARM::tPOP) {
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// The first two operands are predicates. The last two are
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// imp-def and imp-use of SP. Check everything in between.
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for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
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if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
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return false;
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return true;
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}
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// Or if this is a fp reg spill.
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if (MI->getOpcode() == (int)ARM::VLDRD &&
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return ((MI->getOpcode() == (int)ARM::VLDRD ||
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MI->getOpcode() == (int)ARM::LDRi12 ||
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MI->getOpcode() == (int)ARM::t2LDRi12) &&
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MI->getOperand(1).isFI() &&
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
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return true;
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return false;
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
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}
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void ARMBaseRegisterInfo::
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@ -1957,8 +1945,12 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
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// Move SP to start of integer callee save spill area 1.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::tPOP, 0, 2, STI);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
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// Move SP to SP upon entry to the function.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
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}
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if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
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@ -44,20 +44,6 @@ static inline bool isARMLowRegister(unsigned Reg) {
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}
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}
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/// isARMPushRegister - Returns true if the register is a low register (r0-r7)
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/// or a stack/pc register that we should push/pop.
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static inline bool isARMPushRegister(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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case LR: case SP: case PC:
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return true;
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default:
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return false;
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}
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}
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class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
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protected:
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const ARMBaseInstrInfo &TII;
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@ -148,7 +148,7 @@ bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
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if (!Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass(true));
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return true;
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@ -157,12 +157,11 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass());
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if (Subtarget.hasNEON())
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if (OptLevel != CodeGenOpt::None && Subtarget.hasNEON())
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PM.add(createNEONMoveFixPass());
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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