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https://github.com/c64scene-ar/llvm-6502.git
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Revert r191393 since it caused pr17380.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
30ec8a3658
commit
6c73cf5a8a
@ -3748,26 +3748,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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}
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}
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// fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
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// Only fold this if the inner zext has no other uses to avoid increasing
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// the total number of instructions.
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if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
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N0.getOperand(0).getOpcode() == ISD::SRL &&
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isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
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uint64_t c1 =
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cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
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if (c1 < VT.getSizeInBits()) {
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uint64_t c2 = N1C->getZExtValue();
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if (c1 == c2) {
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SDValue NewOp0 = N0.getOperand(0);
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EVT ShiftVT = NewOp0.getValueType();
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SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), ShiftVT,
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NewOp0, DAG.getConstant(c2, ShiftVT));
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
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}
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}
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}
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// fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
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// (and (srl x, (sub c1, c2), MASK)
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// Only fold this if the inner shift has no other uses -- if it does, folding
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@ -1,181 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
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; fold (shl (zext (lshr (A, X))), X) -> (zext (shl (lshr (A, X)), X))
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; Canolicalize the sequence shl/zext/lshr performing the zeroextend
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; as the last instruction of the sequence.
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; This will help DAGCombiner to identify and then fold the sequence
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; of shifts into a single AND.
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; This transformation is profitable if the shift amounts are the same
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; and if there is only one use of the zext.
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define i16 @fun1(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i16
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%shl = shl i16 %ext, 4
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ret i16 %shl
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}
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; CHECK-LABEL: @fun1
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i32 @fun2(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i32
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%shl = shl i32 %ext, 4
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ret i32 %shl
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}
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; CHECK-LABEL: @fun2
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i32 @fun3(i16 zeroext %v) {
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entry:
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%shr = lshr i16 %v, 4
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%ext = zext i16 %shr to i32
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%shl = shl i32 %ext, 4
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ret i32 %shl
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}
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; CHECK-LABEL: @fun3
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i64 @fun4(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun4
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i64 @fun5(i16 zeroext %v) {
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entry:
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%shr = lshr i16 %v, 4
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%ext = zext i16 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun5
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i64 @fun6(i32 zeroext %v) {
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entry:
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%shr = lshr i32 %v, 4
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun6
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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; Don't fold the pattern if we use arithmetic shifts.
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define i64 @fun7(i8 zeroext %v) {
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entry:
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%shr = ashr i8 %v, 4
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%ext = zext i8 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun7
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; CHECK: sar
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; CHECK: shl
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; CHECK: ret
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define i64 @fun8(i16 zeroext %v) {
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entry:
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%shr = ashr i16 %v, 4
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%ext = zext i16 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun8
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; CHECK: sar
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; CHECK: shl
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; CHECK: ret
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define i64 @fun9(i32 zeroext %v) {
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entry:
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%shr = ashr i32 %v, 4
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun9
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; CHECK: sar
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; CHECK: shl
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; CHECK: ret
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; Don't fold the pattern if there is more than one use of the
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; operand in input to the shift left.
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define i64 @fun10(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i64
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%shl = shl i64 %ext, 4
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%add = add i64 %shl, %ext
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ret i64 %add
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}
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; CHECK-LABEL: @fun10
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; CHECK: shr
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; CHECK: shl
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; CHECK: ret
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define i64 @fun11(i16 zeroext %v) {
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entry:
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%shr = lshr i16 %v, 4
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%ext = zext i16 %shr to i64
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%shl = shl i64 %ext, 4
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%add = add i64 %shl, %ext
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ret i64 %add
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}
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; CHECK-LABEL: @fun11
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; CHECK: shr
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; CHECK: shl
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; CHECK: ret
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define i64 @fun12(i32 zeroext %v) {
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entry:
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%shr = lshr i32 %v, 4
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 4
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%add = add i64 %shl, %ext
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ret i64 %add
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}
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; CHECK-LABEL: @fun12
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; CHECK: shr
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; CHECK: shl
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; CHECK: ret
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