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Fix some uses of getSubRegisters() to use getSubReg() instead.

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It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157703 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-05-30 18:40:49 +00:00
parent 275fd2523e
commit 6c823822cd
3 changed files with 13 additions and 10 deletions
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2
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -189,7 +189,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(MI.getOpcode() == Hexagon::LDriw_f) ||
(MI.getOpcode() == Hexagon::LDrid_f)) {
unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
*getSubRegisters(MI.getOperand(0).getReg()) :
getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
MI.getOperand(0).getReg();
// Check if offset can fit in addi.

5
lib/Target/Mips/MipsFrameLowering.cpp
View File

@ -196,11 +196,10 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
// If Reg is a double precision register, emit two cfa_offsets,
// one for each of the paired single precision registers.
if (Mips::AFGR64RegClass.contains(Reg)) {
const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg);
MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
MachineLocation SrcML0(*SubRegs);
MachineLocation SrcML1(*(SubRegs + 1));
MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
if (!STI.isLittle())
std::swap(SrcML0, SrcML1);

16
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -240,9 +240,12 @@ void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
unsigned N = I->getOperand(2).getImm();
const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
DebugLoc dl = I->getDebugLoc();
const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
assert(N < 2 && "Invalid immediate");
unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx);
BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
}
void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
@ -252,13 +255,14 @@ void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc();
const uint16_t* SubReg =
TM.getRegisterInfo()->getSubRegisters(DstReg);
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
// mtc1 Lo, $fp
// mtc1 Hi, $fp + 1
BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven))
.addReg(LoReg);
BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd))
.addReg(HiReg);
}
bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {