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Add the beginnings of an implementatation of lazy liveness analysis, based on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al.
This is still very early, hasn't been tested, and is not yet well documented. More to come soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73141 91177308-0d34-0410-b5e6-96231b3b80d8
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include/llvm/CodeGen/LazyLiveness.h
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include/llvm/CodeGen/LazyLiveness.h
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//===- LazyLiveness.h - Lazy, CFG-invariant liveness information ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass implements a lazy liveness analysis as per "Fast Liveness Checking
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// for SSA-form Programs," by Boissinot, et al.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LAZYLIVENESS_H
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#define LLVM_CODEGEN_LAZYLIVENESS_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SparseBitVector.h"
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#include <vector>
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namespace llvm {
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class MachineRegisterInfo;
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class LazyLiveness : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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LazyLiveness() : MachineFunctionPass(&ID) { }
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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AU.addRequired<MachineDominatorTree>();
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}
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bool runOnMachineFunction(MachineFunction &mf);
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bool vregLiveIntoMBB(unsigned vreg, MachineBasicBlock* MBB);
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private:
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void computeBackedgeChain(MachineFunction& mf, MachineBasicBlock* MBB);
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typedef std::pair<MachineBasicBlock*, MachineBasicBlock*> edge_t;
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MachineRegisterInfo* MRI;
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DenseMap<MachineBasicBlock*, unsigned> preorder;
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std::vector<MachineBasicBlock*> rev_preorder;
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DenseMap<MachineBasicBlock*, SparseBitVector<128> > rv;
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DenseMap<MachineBasicBlock*, SparseBitVector<128> > tv;
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DenseSet<edge_t> backedges;
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SparseBitVector<128> backedge_source;
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SparseBitVector<128> backedge_target;
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SparseBitVector<128> calculated;
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};
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}
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#endif
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153
lib/CodeGen/LazyLiveness.cpp
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lib/CodeGen/LazyLiveness.cpp
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//===- LazyLiveness.cpp - Lazy, CFG-invariant liveness information --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass implements a lazy liveness analysis as per "Fast Liveness Checking
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// for SSA-form Programs," by Boissinot, et al.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "lazyliveness"
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#include "llvm/CodeGen/LazyLiveness.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/PostOrderIterator.h"
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using namespace llvm;
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char LazyLiveness::ID = 0;
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void LazyLiveness::computeBackedgeChain(MachineFunction& mf,
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MachineBasicBlock* MBB) {
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SparseBitVector<128> tmp = rv[MBB];
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tmp.set(preorder[MBB]);
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tmp &= backedge_source;
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calculated.set(preorder[MBB]);
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for (SparseBitVector<128>::iterator I = tmp.begin(); I != tmp.end(); ++I) {
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MachineBasicBlock* SrcMBB = rev_preorder[*I];
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for (MachineBasicBlock::succ_iterator SI = SrcMBB->succ_begin();
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SI != SrcMBB->succ_end(); ++SI) {
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MachineBasicBlock* TgtMBB = *SI;
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if (backedges.count(std::make_pair(SrcMBB, TgtMBB)) &&
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!rv[MBB].test(preorder[TgtMBB])) {
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if (!calculated.test(preorder[TgtMBB]))
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computeBackedgeChain(mf, TgtMBB);
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tv[MBB].set(preorder[TgtMBB]);
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tv[MBB] |= tv[TgtMBB];
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}
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}
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tv[MBB].reset(preorder[MBB]);
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}
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}
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bool LazyLiveness::runOnMachineFunction(MachineFunction &mf) {
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rv.clear();
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tv.clear();
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backedges.clear();
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backedge_source.clear();
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backedge_target.clear();
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calculated.clear();
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preorder.clear();
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MRI = &mf.getRegInfo();
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// Step 0: Compute preorder numbering for all MBBs.
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unsigned num = 0;
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for (df_iterator<MachineBasicBlock*> DI = df_begin(&*mf.begin());
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DI != df_end(&*mf.end()); ++DI) {
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preorder[*DI] = num++;
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rev_preorder.push_back(*DI);
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}
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// Step 1: Compute the transitive closure of the CFG, ignoring backedges.
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for (po_iterator<MachineBasicBlock*> POI = po_begin(&*mf.begin());
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POI != po_end(&*mf.begin()); ++POI) {
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MachineBasicBlock* MBB = *POI;
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SparseBitVector<128>& entry = rv[MBB];
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entry.set(preorder[MBB]);
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
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SI != MBB->succ_end(); ++SI) {
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DenseMap<MachineBasicBlock*, SparseBitVector<128> >::iterator SII =
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rv.find(*SI);
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// Because we're iterating in postorder, any successor that does not yet
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// have an rv entry must be on a backedge.
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if (SII != rv.end()) {
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entry |= SII->second;
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} else {
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backedges.insert(std::make_pair(MBB, *SI));
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backedge_source.set(preorder[MBB]);
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backedge_target.set(preorder[*SI]);
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}
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}
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}
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for (SparseBitVector<128>::iterator I = backedge_source.begin();
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I != backedge_source.end(); ++I)
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computeBackedgeChain(mf, rev_preorder[*I]);
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for (po_iterator<MachineBasicBlock*> POI = po_begin(&*mf.begin()),
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POE = po_end(&*mf.begin()); POI != POE; ++POI)
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if (!backedge_target.test(preorder[*POI]))
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for (MachineBasicBlock::succ_iterator SI = (*POI)->succ_begin();
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SI != (*POI)->succ_end(); ++SI)
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if (!backedges.count(std::make_pair(*POI, *SI)) && tv.count(*SI))
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tv[*POI]= tv[*SI];
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for (po_iterator<MachineBasicBlock*> POI = po_begin(&*mf.begin()),
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POE = po_end(&*mf.begin()); POI != POE; ++POI)
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tv[*POI].set(preorder[*POI]);
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return false;
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}
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bool LazyLiveness::vregLiveIntoMBB(unsigned vreg, MachineBasicBlock* MBB) {
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MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
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MachineBasicBlock* DefMBB = MRI->def_begin(vreg)->getParent();
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unsigned def = preorder[DefMBB];
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unsigned max_dom = 0;
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for (df_iterator<MachineDomTreeNode*> DI = df_begin(MDT[DefMBB]);
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DI != df_end(MDT[DefMBB]); ++DI)
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if (preorder[DI->getBlock()] > max_dom) {
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max_dom = preorder[(*DI)->getBlock()];
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}
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if (preorder[MBB] <= def || max_dom < preorder[MBB])
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return false;
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SparseBitVector<128>::iterator I = tv[MBB].begin();
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while (I != tv[MBB].end() && *I <= def) ++I;
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while (I != tv[MBB].end() && *I < max_dom) {
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(vreg);
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UI != MachineRegisterInfo::use_end(); ++UI) {
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MachineBasicBlock* UseMBB = UI->getParent();
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if (rv[rev_preorder[*I]].test(preorder[UseMBB]))
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return true;
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unsigned t_dom = 0;
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for (df_iterator<MachineDomTreeNode*> DI =
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df_begin(MDT[rev_preorder[*I]]);
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DI != df_end(MDT[rev_preorder[*I]]); ++DI)
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if (preorder[DI->getBlock()] > t_dom) {
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max_dom = preorder[(*DI)->getBlock()];
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}
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I = tv[MBB].begin();
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while (I != tv[MBB].end() && *I < t_dom) ++I;
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}
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}
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return false;
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}
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