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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Propagate debug loc info for some of the *_EXTEND functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63434 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -376,6 +376,7 @@ public:
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/// getZeroExtendInReg - Return the expression required to zero extend the Op
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/// value assuming it was the smaller SrcTy value.
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SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
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SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
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/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
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SDValue getNOT(SDValue Val, MVT VT);
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@ -2914,7 +2914,7 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
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// Fold to a simpler select_cc
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if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
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return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
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return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
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SCC.getOperand(0), SCC.getOperand(1), N2, N3,
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SCC.getOperand(2));
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@ -3006,12 +3006,13 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// fold (sext c1) -> c1
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if (isa<ConstantSDNode>(N0))
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return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
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return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
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// fold (sext (sext x)) -> (sext x)
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// fold (sext (aext x)) -> (sext x)
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if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
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return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
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return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
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N0.getOperand(0));
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if (N0.getOpcode() == ISD::TRUNCATE) {
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// fold (sext (truncate (load x))) -> (sext (smaller load x))
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@ -3020,7 +3021,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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if (NarrowLoad.getNode()) {
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if (NarrowLoad.getNode() != N0.getNode())
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CombineTo(N0.getNode(), NarrowLoad);
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return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
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return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
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}
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// See if the value being truncated is already sign extended. If so, just
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@ -3040,22 +3041,22 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
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// bits, just sext from i32.
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if (NumSignBits > OpBits-MidBits)
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return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
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return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
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} else {
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// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
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// bits, just truncate to i32.
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if (NumSignBits > OpBits-MidBits)
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return DAG.getNode(ISD::TRUNCATE, VT, Op);
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return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
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}
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// fold (sext (truncate x)) -> (sextinreg x).
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if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
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N0.getValueType())) {
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if (Op.getValueType().bitsLT(VT))
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Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
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Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
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else if (Op.getValueType().bitsGT(VT))
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Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
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Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
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DAG.getValueType(N0.getValueType()));
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}
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}
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@ -3070,29 +3071,37 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
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if (DoXform) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(),
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VT, LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(),
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N0.getValueType(),
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LN0->isVolatile(), LN0->getAlignment());
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CombineTo(N, ExtLoad);
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
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N0.getValueType(), ExtLoad);
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CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
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// Extend SetCC uses if necessary.
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for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
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SDNode *SetCC = SetCCs[i];
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SmallVector<SDValue, 4> Ops;
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for (unsigned j = 0; j != 2; ++j) {
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SDValue SOp = SetCC->getOperand(j);
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if (SOp == Trunc)
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Ops.push_back(ExtLoad);
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else
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Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
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Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(),
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VT, SOp));
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}
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Ops.push_back(SetCC->getOperand(2));
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(),
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SetCC->getValueType(0),
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&Ops[0], Ops.size()));
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}
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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@ -3105,19 +3114,21 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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MVT EVT = LN0->getMemoryVT();
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if ((!LegalOperations && !LN0->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
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LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(), EVT,
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LN0->isVolatile(), LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N0.getNode(),
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DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
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N0.getValueType(), ExtLoad),
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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// sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
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// sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
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if (N0.getOpcode() == ISD::SETCC) {
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SDValue SCC =
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SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
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@ -3129,7 +3140,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// fold (sext x) -> (zext x) if the sign bit is known zero.
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if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
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DAG.SignBitIsZero(N0))
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return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
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return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
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return SDValue();
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}
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@ -3140,11 +3151,12 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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// fold (zext c1) -> c1
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if (isa<ConstantSDNode>(N0))
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return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
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return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
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// fold (zext (zext x)) -> (zext x)
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// fold (zext (aext x)) -> (zext x)
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if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
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return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
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return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
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N0.getOperand(0));
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// fold (zext (truncate (load x))) -> (zext (smaller load x))
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// fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
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@ -3153,7 +3165,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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if (NarrowLoad.getNode()) {
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if (NarrowLoad.getNode() != N0.getNode())
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CombineTo(N0.getNode(), NarrowLoad);
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return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
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return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
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}
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}
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@ -3162,11 +3174,11 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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(!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
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SDValue Op = N0.getOperand(0);
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if (Op.getValueType().bitsLT(VT)) {
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Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
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Op = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, Op);
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} else if (Op.getValueType().bitsGT(VT)) {
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Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
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Op = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, Op);
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}
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return DAG.getZeroExtendInReg(Op, N0.getValueType());
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return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
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}
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// fold (zext (and (trunc x), cst)) -> (and x, cst).
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@ -3175,13 +3187,14 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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SDValue X = N0.getOperand(0).getOperand(0);
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if (X.getValueType().bitsLT(VT)) {
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X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
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X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X);
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} else if (X.getValueType().bitsGT(VT)) {
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X = DAG.getNode(ISD::TRUNCATE, VT, X);
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X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X);
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}
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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Mask.zext(VT.getSizeInBits());
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return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
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return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
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X, DAG.getConstant(Mask, VT));
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}
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// fold (zext (load x)) -> (zext (truncate (zextload x)))
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@ -3194,18 +3207,22 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
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if (DoXform) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
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LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(),
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N0.getValueType(),
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LN0->isVolatile(), LN0->getAlignment());
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CombineTo(N, ExtLoad);
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
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N0.getValueType(), ExtLoad);
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CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
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// Extend SetCC uses if necessary.
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for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
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SDNode *SetCC = SetCCs[i];
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SmallVector<SDValue, 4> Ops;
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for (unsigned j = 0; j != 2; ++j) {
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SDValue SOp = SetCC->getOperand(j);
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if (SOp == Trunc)
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@ -3213,10 +3230,13 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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else
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Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
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}
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Ops.push_back(SetCC->getOperand(2));
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(),
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SetCC->getValueType(0),
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&Ops[0], Ops.size()));
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}
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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@ -3229,13 +3249,15 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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MVT EVT = LN0->getMemoryVT();
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if ((!LegalOperations && !LN0->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
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LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(), EVT,
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LN0->isVolatile(), LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N0.getNode(),
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DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
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ExtLoad),
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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@ -831,6 +831,14 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
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getConstant(Imm, Op.getValueType()));
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}
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SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
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if (Op.getValueType() == VT) return Op;
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APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
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VT.getSizeInBits());
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return getNode(ISD::AND, DL, Op.getValueType(), Op,
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getConstant(Imm, Op.getValueType()));
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}
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/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
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///
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SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) {
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