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Fix handling of FP constants with single precision, and loading of internal linkage function addresses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15742 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -624,9 +624,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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.addConstantPoolIndex(CPI);
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BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1)
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.addConstantPoolIndex(CPI);
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unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
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BuildMI(*MBB, IP, LoadOpcode, 2, R).addSImm(0).addReg(Reg2);
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BuildMI(*MBB, IP, PPC::LFD, 2, R).addSImm(0).addReg(Reg2);
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} else if (isa<ConstantPointerNull>(C)) {
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// Copy zero (null pointer) to the register.
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BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
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@ -634,7 +632,8 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// GV is located at base + distance
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unsigned GlobalBase = makeAnotherReg(Type::IntTy);
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unsigned TmpReg = makeAnotherReg(GV->getType());
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unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()) ?
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unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()
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|| dyn_cast<Function>(GV)) ?
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PPC::LOADLoIndirect : PPC::LOADLoDirect;
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// Move value at base + distance into return reg
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@ -1809,6 +1808,11 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned DestReg) {
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static const unsigned OpcodeTab[][4] = {
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{ PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
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{ PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
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};
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// Special case: op Reg, <const fp>
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if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
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// Create a constant pool entry for this constant.
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@ -1817,15 +1821,16 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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const Type *Ty = Op1->getType();
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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static const unsigned OpcodeTab[][4] = {
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{ PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
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{ PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
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};
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unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
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unsigned Opcode = OpcodeTab[1][OperatorClass];
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unsigned Op1Reg = getReg(Op1C, BB, IP);
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unsigned Op0r = getReg(Op0, BB, IP);
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BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1Reg);
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unsigned Op0Reg = getReg(Op0, BB, IP);
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if (Ty == Type::DoubleTy) {
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BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
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} else {
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unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
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BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
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}
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return;
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}
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@ -1837,32 +1842,27 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
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return;
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} else {
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// R1 = op CST, R2 --> R1 = opr R2, CST
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// Create a constant pool entry for this constant.
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MachineConstantPool *CP = F->getConstantPool();
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unsigned CPI = CP->getConstantPoolIndex(Op0C);
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const Type *Ty = Op0C->getType();
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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static const unsigned OpcodeTab[][4] = {
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{ PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
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{ PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
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};
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unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
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unsigned Opcode = OpcodeTab[1][OperatorClass];
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unsigned Op0Reg = getReg(Op0C, BB, IP);
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unsigned Op1Reg = getReg(Op1, BB, IP);
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BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
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if (Ty == Type::DoubleTy) {
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BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
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} else {
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unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
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BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
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}
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return;
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}
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// General case.
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static const unsigned OpcodeTab[] = {
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PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV
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};
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unsigned Opcode = OpcodeTab[OperatorClass];
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unsigned Opcode = OpcodeTab[Op0->getType() != Type::FloatTy][OperatorClass];
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//unsigned Opcode = OpcodeTab[OperatorClass];
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(Op1, BB, IP);
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BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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