6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-02 09:33:59 +00:00
Code Issues Projects Releases Wiki Activity

Revert r137562 because it caused PR10674

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-08-16 14:34:29 +00:00
parent 7a817eae6c
commit 6d1f5d951b
1 changed files with 0 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -928,13 +928,6 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
assert(Val.getBitWidth() == EltVT.getSizeInBits() && assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
"APInt size does not match type size!"); "APInt size does not match type size!");
// In some cases the vector type is legal but the element type is illegal.
// In this case, promote the inserted value. The type does not need to match
// the vector element type. Any extra bits introduced will be
// truncated away.
if (VT.isVector())
EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
FoldingSetNodeID ID; FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);