mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add instruction formats and few opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76062 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
6ff3f2c710
commit
6d4b270e38
@ -7,528 +7,121 @@
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//
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//===----------------------------------------------------------------------===//
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class InstSystemZ<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo : Format<0>;
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def EForm : Format<1>;
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def IForm : Format<2>;
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def RIForm : Format<3>;
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def RIEForm : Format<4>;
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def RILForm : Format<5>;
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def RISForm : Format<6>;
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def RRForm : Format<7>;
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def RREForm : Format<8>;
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def RRFForm : Format<9>;
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def RRRForm : Format<10>;
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def RRSForm : Format<11>;
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def RSForm : Format<12>;
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def RSIForm : Format<13>;
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def RSILForm : Format<14>;
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def RSYForm : Format<15>;
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def RXForm : Format<16>;
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def RXEForm : Format<17>;
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def RXFForm : Format<18>;
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def RXYForm : Format<19>;
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def SForm : Format<20>;
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def SIForm : Format<21>;
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def SILForm : Format<22>;
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def SIYForm : Format<23>;
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def SSForm : Format<24>;
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def SSEForm : Format<25>;
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def SSFForm : Format<26>;
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class InstSystemZ<bits<16> op, Format f, dag outs, dag ins> : Instruction {
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let Namespace = "SystemZ";
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bits<16> Opcode = op;
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Format Form = f;
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bits<5> FormBits = Form.Value;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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}
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class I8<bits<8> op, Format f, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSystemZ<0, f, outs, ins> {
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let Opcode{0-7} = op;
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let Opcode{8-15} = 0;
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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//===----------------------------------------------------------------------===//
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// E format
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//===----------------------------------------------------------------------===//
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class I12<bits<12> op, Format f, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSystemZ<0, f, outs, ins> {
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let Opcode{0-11} = op;
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let Opcode{12-15} = 0;
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class F_E<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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let Inst{15-0} = opcode;
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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//===----------------------------------------------------------------------===//
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// I format
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//===----------------------------------------------------------------------===//
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class F_I<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-32} = opcode;
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//let Inst{31-0} = simm32;
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class I16<bits<16> op, Format f, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSystemZ<op, f, outs, ins> {
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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//===----------------------------------------------------------------------===//
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// RR format
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//===----------------------------------------------------------------------===//
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class RRI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, RRForm, outs, ins, asmstr, pattern>;
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class F_RR<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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class RII<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I12<op, RIForm, outs, ins, asmstr, pattern>;
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field bits<16> Inst;
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class RILI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I12<op, RILForm, outs, ins, asmstr, pattern>;
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let Inst{15-8} = opcode;
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}
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class RREI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, RREForm, outs, ins, asmstr, pattern>;
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//===----------------------------------------------------------------------===//
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// RRE format
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//===----------------------------------------------------------------------===//
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class RXI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, RXForm, outs, ins, asmstr, pattern>;
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class F_RRE<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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class RXYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, RXYForm, outs, ins, asmstr, pattern>;
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field bits<32> Inst;
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class RSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, RSForm, outs, ins, asmstr, pattern>;
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let Inst{31-16} = opcode;
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let Inst{15-8} = 0;
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//let Inst{7-4} = r1;
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//let Inst{3-0} = r2;
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}
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class RSYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, RSYForm, outs, ins, asmstr, pattern>;
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//===----------------------------------------------------------------------===//
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// RRF format (1)
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//===----------------------------------------------------------------------===//
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class SII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, SIForm, outs, ins, asmstr, pattern>;
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class F_RRF_1<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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class SIYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, SIYForm, outs, ins, asmstr, pattern>;
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field bits<32> Inst;
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class SILI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, SILForm, outs, ins, asmstr, pattern>;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = r1;
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let Inst{11-8} = 0;
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//let Inst{7-4} = r3;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RRF format (2)
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//===----------------------------------------------------------------------===//
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class F_RRF_2<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = m3;
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let Inst{11-8} = 0;
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//let Inst{7-4} = r1;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RRF format (3)
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//===----------------------------------------------------------------------===//
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class F_RRF_3<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = r3;
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//let Inst{11-8} = m4;
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//let Inst{7-4} = r1;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RX format
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//===----------------------------------------------------------------------===//
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class F_RX<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = x2;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RXE format
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//===----------------------------------------------------------------------===//
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class F_RXE<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = x2;
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//let Inst{31-28} = b2;
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//let Inst{27-16} = udisp12;
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let Inst{15-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RXF format
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//===----------------------------------------------------------------------===//
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class F_RXF<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r3;
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//let Inst{35-32} = x2;
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//let Inst{31-28} = b2;
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//let Inst{27-16} = udisp12;
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//let Inst{15-11} = r1;
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let Inst{11-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RXY format
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//===----------------------------------------------------------------------===//
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class F_RXY<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = x2;
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//let Inst{31-28} = b2;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RS format (1)
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//===----------------------------------------------------------------------===//
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class F_RS_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = r3;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RS format (2)
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//===----------------------------------------------------------------------===//
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class F_RS_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = m3;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RS format (3)
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//===----------------------------------------------------------------------===//
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class F_RS_3<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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let Inst{19-16} = 0;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RSY format (1)
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//===----------------------------------------------------------------------===//
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class F_RSY_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = r3;
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//let Inst{31-28} = b2;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RSY format (2)
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//===----------------------------------------------------------------------===//
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class F_RSY_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = m3;
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//let Inst{31-28} = b2;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RSL format
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//===----------------------------------------------------------------------===//
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class F_RSL<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = ll;
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let Inst{35-32} = 0;
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//let Inst{31-28} = b1;
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//let Inst{27-16} = udisp12;
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let Inst{15-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RSI format
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//===----------------------------------------------------------------------===//
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class F_RSI<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = r3;
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//let Inst{15-0} = simm16;
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}
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//===----------------------------------------------------------------------===//
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// RI format
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//===----------------------------------------------------------------------===//
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class F_RI<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = op2;
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//let Inst{15-0} = simm16;
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}
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//===----------------------------------------------------------------------===//
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// RIE format
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//===----------------------------------------------------------------------===//
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class F_RIE<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = r2;
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//let Inst{31-16} = simm16;
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let Inst{15-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RIL format (1)
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//===----------------------------------------------------------------------===//
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class F_RIL_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = op2;
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//let Inst{31-0} = simm32;
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}
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//===----------------------------------------------------------------------===//
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// RIL format (2)
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//===----------------------------------------------------------------------===//
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class F_RIL_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = m1;
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//let Inst{35-32} = op2;
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//let Inst{31-0} = simm32;
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}
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//===----------------------------------------------------------------------===//
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// SI format
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//===----------------------------------------------------------------------===//
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class F_SI<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
|
||||
|
||||
let Inst{31-24} = opcode;
|
||||
//let Inst{23-16} = simm8;
|
||||
//let Inst{15-12} = b1;
|
||||
//let Inst{11-0} = udisp12;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SIY format
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_SIY<bits<8> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<48> Inst;
|
||||
|
||||
let Inst{47-40} = opcode;
|
||||
//let Inst{39-32} = simm8;
|
||||
//let Inst{31-28} = b1;
|
||||
//let Inst{27-8} = sdisp20;
|
||||
//let Inst{7-0} = op2;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// S format
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_S<bits<16> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<32> Inst;
|
||||
|
||||
let Inst{31-16} = opcode;
|
||||
//let Inst{15-12} = b2;
|
||||
//let Inst{11-0} = udisp12;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SS format (1)
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_SS_1<bits<8> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<48> Inst;
|
||||
|
||||
let Inst{47-40} = opcode;
|
||||
//let Inst{39-32} = ll;
|
||||
//let Inst{31-28} = b1;
|
||||
//let Inst{27-16} = udisp12;
|
||||
//let Inst{15-12} = b2;
|
||||
//let Inst{11-0} = udisp12_2;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SS format (2)
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_SS_2<bits<8> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<48> Inst;
|
||||
|
||||
let Inst{47-40} = opcode;
|
||||
//let Inst{39-36} = l1;
|
||||
//let Inst{35-32} = l2;
|
||||
//let Inst{31-28} = b1;
|
||||
//let Inst{27-16} = udisp12;
|
||||
//let Inst{15-12} = b2;
|
||||
//let Inst{11-0} = udisp12_2;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SS format (3)
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_SS_3<bits<8> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<48> Inst;
|
||||
|
||||
let Inst{47-40} = opcode;
|
||||
//let Inst{39-36} = r1;
|
||||
//let Inst{35-32} = r3;
|
||||
//let Inst{31-28} = b1;
|
||||
//let Inst{27-16} = udisp12;
|
||||
//let Inst{15-12} = b2;
|
||||
//let Inst{11-0} = udisp12_2;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SS format (4)
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_SS_4<bits<8> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<48> Inst;
|
||||
|
||||
let Inst{47-40} = opcode;
|
||||
//let Inst{39-36} = r1;
|
||||
//let Inst{35-32} = r3;
|
||||
//let Inst{31-28} = b2;
|
||||
//let Inst{27-16} = udisp12_2;
|
||||
//let Inst{15-12} = b4;
|
||||
//let Inst{11-0} = udisp12_4;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SSE format
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class F_SSE<bits<16> opcode,
|
||||
dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
|
||||
field bits<48> Inst;
|
||||
|
||||
let Inst{47-32} = opcode;
|
||||
//let Inst{31-28} = b1;
|
||||
//let Inst{27-16} = udisp12;
|
||||
//let Inst{15-12} = b2;
|
||||
//let Inst{11-0} = udisp12_2;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pseudo instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSystemZ<outs, ins, asmstr, pattern> {
|
||||
: InstSystemZ<0, Pseudo, outs, ins> {
|
||||
|
||||
let Pattern = pattern;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user