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Reversed the order of the llvm.writeport() operands so that the value

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is listed first and the address is listed second.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12795 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
John Criswell 2004-04-09 19:09:14 +00:00
parent 2eefe518de
commit 6d804f408a
3 changed files with 14 additions and 14 deletions
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12
lib/Target/X86/InstSelectSimple.cpp
View File

@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
// acceptable range for this architecture.
//
//
if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {
std::cerr << "llvm.writeport: Address size is not 16 bits\n";
exit (1);
}
@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
// Now, move the I/O port address into the DX register and the value to
// write into the AL/AX/EAX register.
//
BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {
case 1:
BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT8, 0);
break;
case 2:
BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT16, 0);
break;
case 4:
BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT32, 0);
break;
default:

12
lib/Target/X86/X86ISelSimple.cpp
View File

@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
// acceptable range for this architecture.
//
//
if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {
std::cerr << "llvm.writeport: Address size is not 16 bits\n";
exit (1);
}
@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
// Now, move the I/O port address into the DX register and the value to
// write into the AL/AX/EAX register.
//
BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {
case 1:
BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT8, 0);
break;
case 2:
BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT16, 0);
break;
case 4:
BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT32, 0);
break;
default:

4
lib/VMCore/Verifier.cpp
View File

@ -611,9 +611,9 @@ void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI) {
case Intrinsic::writeport:
Assert1(FT->getNumParams() == 2,
"Illegal # arguments for intrinsic function!", IF);
Assert1(FT->getParamType(0)->isUnsigned(),
Assert1(FT->getParamType(0)->isIntegral(),
"First argument not unsigned int!", IF);
Assert1(FT->getParamType(1)->isIntegral(),
Assert1(FT->getParamType(1)->isUnsigned(),
"First argument not unsigned int!", IF);
NumArgs = 2;
break;