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Reversed the order of the llvm.writeport() operands so that the value
is listed first and the address is listed second. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12795 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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// acceptable range for this architecture.
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//
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//
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if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
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if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {
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std::cerr << "llvm.writeport: Address size is not 16 bits\n";
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exit (1);
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}
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@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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// Now, move the I/O port address into the DX register and the value to
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// write into the AL/AX/EAX register.
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//
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BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
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switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
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BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
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switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {
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case 1:
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BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
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BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));
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BuildMI(BB, X86::OUT8, 0);
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break;
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case 2:
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BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
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BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));
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BuildMI(BB, X86::OUT16, 0);
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break;
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case 4:
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));
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BuildMI(BB, X86::OUT32, 0);
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break;
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default:
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@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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// acceptable range for this architecture.
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//
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//
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if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
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if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {
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std::cerr << "llvm.writeport: Address size is not 16 bits\n";
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exit (1);
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}
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@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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// Now, move the I/O port address into the DX register and the value to
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// write into the AL/AX/EAX register.
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//
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BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
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switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
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BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
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switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {
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case 1:
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BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
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BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));
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BuildMI(BB, X86::OUT8, 0);
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break;
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case 2:
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BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
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BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));
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BuildMI(BB, X86::OUT16, 0);
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break;
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case 4:
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));
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BuildMI(BB, X86::OUT32, 0);
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break;
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default:
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@ -611,9 +611,9 @@ void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI) {
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case Intrinsic::writeport:
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Assert1(FT->getNumParams() == 2,
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"Illegal # arguments for intrinsic function!", IF);
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Assert1(FT->getParamType(0)->isUnsigned(),
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Assert1(FT->getParamType(0)->isIntegral(),
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"First argument not unsigned int!", IF);
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Assert1(FT->getParamType(1)->isIntegral(),
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Assert1(FT->getParamType(1)->isUnsigned(),
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"First argument not unsigned int!", IF);
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NumArgs = 2;
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break;
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