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Add addrmode5 fp load support. Swap float/thumb operand adding to handle

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thumb with floating point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-09-18 01:59:37 +00:00
parent b74558ad3e
commit 6dab137b88
1 changed files with 22 additions and 6 deletions
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28
lib/Target/ARM/ARMFastISel.cpp
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@ -555,6 +555,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
assert(VT.isSimple() && "Non-simple types are invalid here!"); assert(VT.isSimple() && "Non-simple types are invalid here!");
unsigned Opc; unsigned Opc;
bool isFloat = false;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
default: default:
assert(false && "Trying to emit for an unhandled type!"); assert(false && "Trying to emit for an unhandled type!");
@ -570,13 +571,27 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
case MVT::i32: case MVT::i32:
Opc = isThumb ? ARM::tLDR : ARM::LDR; Opc = isThumb ? ARM::tLDR : ARM::LDR;
break; break;
case MVT::f32:
Opc = ARM::VLDRS;
isFloat = true;
break;
case MVT::f64:
Opc = ARM::VLDRD;
isFloat = true;
break;
} }
ResultReg = createResultReg(TLI.getRegClassFor(VT)); ResultReg = createResultReg(TLI.getRegClassFor(VT));
// TODO: Fix the Addressing modes so that these can share some code. // TODO: Fix the Addressing modes so that these can share some code.
// Since this is a Thumb1 load this will work in Thumb1 or 2 mode. // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
if (isThumb) // The thumb addressing mode has operands swapped from the arm addressing
// mode, the floating point one only has two operands.
if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(Reg).addImm(Offset));
else if (isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg) TII.get(Opc), ResultReg)
.addReg(Reg).addImm(Offset).addReg(0)); .addReg(Reg).addImm(Offset).addReg(0));
@ -657,14 +672,15 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
// The thumb addressing mode has operands swapped from the arm addressing // The thumb addressing mode has operands swapped from the arm addressing
// mode, the floating point one only has two operands. // mode, the floating point one only has two operands.
if (isThumb) if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc), SrcReg)
.addReg(DstReg).addImm(Offset).addReg(0));
else if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc), SrcReg) TII.get(StrOpc), SrcReg)
.addReg(DstReg).addImm(Offset)); .addReg(DstReg).addImm(Offset));
else if (isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc), SrcReg)
.addReg(DstReg).addImm(Offset).addReg(0));
else else
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc), SrcReg) TII.get(StrOpc), SrcReg)