6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-28 06:29:45 +00:00
Code Issues Projects Releases Wiki Activity

make mcinstlower remove all but the first operand to CALL64pcrel32.

Browse Source 
The register use operands (e.g. the first argument is passed in a 
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use.  This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.

This fixes rdar://7998435


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104062 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-05-18 21:40:18 +00:00
parent 28dad2a5ca
commit 6db0363bdc
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
View File

@ -329,7 +329,17 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
break;
// CALL64pcrel32 - This instruction has register inputs modeled as normal
// uses instead of implicit uses. As such, truncate off all but the first
// operand (the callee). FIXME: Change isel.
case X86::CALL64pcrel32: {
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(X86::CALL64pcrel32);
OutMI.addOperand(Saved);
break;
}
// The assembler backend wants to see branches in their small form and relax
// them to their large form. The JIT can only handle the large form because