mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Move cmov pseudo instructions to InstrCompiler,
convert all the rest of the cmovs to the multiclass, with good results: X86InstrCMovSetCC.td | 598 +-------------------------------------------------- X86InstrCompiler.td | 61 +++++ 2 files changed, 77 insertions(+), 582 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
25cbf504fe
commit
6dbbff9172
@ -34,7 +34,7 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
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(X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
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}
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"in {
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" in {
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def #NAME#16rm
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: I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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@ -55,588 +55,22 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
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// Conditional Moves.
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defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>;
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defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
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defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>;
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defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
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defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>;
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defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
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defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
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let Constraints = "$src1 = $dst" in {
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// Conditional moves
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let Uses = [EFLAGS] in {
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let Predicates = [HasCMov] in {
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let isCommutable = 1 in {
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovb{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_B, EFLAGS))]>,
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TB, OpSize;
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def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovb{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_B, EFLAGS))]>,
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TB;
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def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovae{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_AE, EFLAGS))]>,
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TB, OpSize;
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def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovae{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_AE, EFLAGS))]>,
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TB;
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def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmove{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_E, EFLAGS))]>,
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TB, OpSize;
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def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmove{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_E, EFLAGS))]>,
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TB;
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def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovne{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_NE, EFLAGS))]>,
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TB, OpSize;
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def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovne{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_NE, EFLAGS))]>,
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TB;
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def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmova{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_A, EFLAGS))]>,
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TB, OpSize;
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def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmova{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_A, EFLAGS))]>,
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TB;
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def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovl{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_L, EFLAGS))]>,
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TB, OpSize;
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def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovl{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_L, EFLAGS))]>,
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TB;
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def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovge{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_GE, EFLAGS))]>,
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TB, OpSize;
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def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovge{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_GE, EFLAGS))]>,
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TB;
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def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovle{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_LE, EFLAGS))]>,
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TB, OpSize;
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def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovle{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_LE, EFLAGS))]>,
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TB;
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def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovg{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_G, EFLAGS))]>,
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TB, OpSize;
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def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovg{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_G, EFLAGS))]>,
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TB;
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def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovs{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_S, EFLAGS))]>,
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TB, OpSize;
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def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovs{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_S, EFLAGS))]>,
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TB;
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def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovns{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_NS, EFLAGS))]>,
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TB, OpSize;
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def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovns{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_NS, EFLAGS))]>,
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TB;
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def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovp{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_P, EFLAGS))]>,
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TB, OpSize;
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def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovp{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_P, EFLAGS))]>,
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TB;
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def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovnp{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_NP, EFLAGS))]>,
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TB, OpSize;
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def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovnp{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_NP, EFLAGS))]>,
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TB;
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def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovo{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_O, EFLAGS))]>,
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TB, OpSize;
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def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovo{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_O, EFLAGS))]>,
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TB;
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def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovno{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_NO, EFLAGS))]>,
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TB, OpSize;
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def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovno{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_NO, EFLAGS))]>,
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TB;
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} // isCommutable = 1
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def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovb{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_B, EFLAGS))]>,
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TB, OpSize;
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def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovb{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_B, EFLAGS))]>,
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TB;
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def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovae{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_AE, EFLAGS))]>,
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TB, OpSize;
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def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovae{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_AE, EFLAGS))]>,
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TB;
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def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmove{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_E, EFLAGS))]>,
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TB, OpSize;
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def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmove{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_E, EFLAGS))]>,
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TB;
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def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovne{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_NE, EFLAGS))]>,
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TB, OpSize;
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def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovne{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_NE, EFLAGS))]>,
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TB;
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def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmova{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_A, EFLAGS))]>,
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TB, OpSize;
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def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmova{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_A, EFLAGS))]>,
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TB;
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def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovl{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_L, EFLAGS))]>,
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TB, OpSize;
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def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovl{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_L, EFLAGS))]>,
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TB;
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def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovge{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_GE, EFLAGS))]>,
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TB, OpSize;
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def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovge{l}\t{$src2, $dst|$dst, $src2}",
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||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovle{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovle{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovg{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovg{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovs{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovs{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovns{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovns{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovp{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovp{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovnp{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovnp{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovo{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_O, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovo{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_O, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovno{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NO, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovno{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NO, EFLAGS))]>,
|
||||
TB;
|
||||
} // Predicates = [HasCMov]
|
||||
|
||||
// X86 doesn't have 8-bit conditional moves. Use a customInserter to
|
||||
// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
|
||||
// however that requires promoting the operands, and can induce additional
|
||||
// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
|
||||
// clobber EFLAGS, because if one of the operands is zero, the expansion
|
||||
// could involve an xor.
|
||||
let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
|
||||
def CMOV_GR8 : I<0, Pseudo,
|
||||
(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
|
||||
"#CMOV_GR8 PSEUDO!",
|
||||
[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
|
||||
imm:$cond, EFLAGS))]>;
|
||||
|
||||
let Predicates = [NoCMov] in {
|
||||
def CMOV_GR32 : I<0, Pseudo,
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
|
||||
"#CMOV_GR32* PSEUDO!",
|
||||
[(set GR32:$dst,
|
||||
(X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
|
||||
def CMOV_GR16 : I<0, Pseudo,
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
|
||||
"#CMOV_GR16* PSEUDO!",
|
||||
[(set GR16:$dst,
|
||||
(X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
|
||||
def CMOV_RFP32 : I<0, Pseudo,
|
||||
(outs RFP32:$dst),
|
||||
(ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
|
||||
"#CMOV_RFP32 PSEUDO!",
|
||||
[(set RFP32:$dst,
|
||||
(X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def CMOV_RFP64 : I<0, Pseudo,
|
||||
(outs RFP64:$dst),
|
||||
(ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
|
||||
"#CMOV_RFP64 PSEUDO!",
|
||||
[(set RFP64:$dst,
|
||||
(X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def CMOV_RFP80 : I<0, Pseudo,
|
||||
(outs RFP80:$dst),
|
||||
(ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
|
||||
"#CMOV_RFP80 PSEUDO!",
|
||||
[(set RFP80:$dst,
|
||||
(X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
} // Predicates = [NoCMov]
|
||||
} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
|
||||
} // Uses = [EFLAGS]
|
||||
|
||||
} // Constraints = "$src1 = $dst" in
|
||||
|
||||
|
||||
// Conditional moves
|
||||
let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
|
||||
let isCommutable = 1 in {
|
||||
def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovb{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovae{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmove{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmova{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovl{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovge{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovle{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovg{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovs{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovns{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovp{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovnp{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NP, EFLAGS))]>, TB;
|
||||
def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovo{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_O, EFLAGS))]>, TB;
|
||||
def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NO, EFLAGS))]>, TB;
|
||||
} // isCommutable = 1
|
||||
|
||||
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovb{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovae{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmove{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmova{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovl{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovge{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovle{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovg{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovs{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovns{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovp{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovnp{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>, TB;
|
||||
def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovo{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_O, EFLAGS))]>, TB;
|
||||
def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NO, EFLAGS))]>, TB;
|
||||
} // Constraints = "$src1 = $dst"
|
||||
defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>;
|
||||
defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>;
|
||||
defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>;
|
||||
defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>;
|
||||
defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>;
|
||||
defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>;
|
||||
defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>;
|
||||
defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>;
|
||||
defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>;
|
||||
|
||||
|
||||
// SetCC instructions.
|
||||
|
||||
@ -273,6 +273,67 @@ def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
|
||||
[(X86TLSCall addr:$sym)]>,
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conditional Move Pseudo Instructions
|
||||
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
|
||||
// Conditional moves
|
||||
let Uses = [EFLAGS] in {
|
||||
|
||||
// X86 doesn't have 8-bit conditional moves. Use a customInserter to
|
||||
// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
|
||||
// however that requires promoting the operands, and can induce additional
|
||||
// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
|
||||
// clobber EFLAGS, because if one of the operands is zero, the expansion
|
||||
// could involve an xor.
|
||||
let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
|
||||
def CMOV_GR8 : I<0, Pseudo,
|
||||
(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
|
||||
"#CMOV_GR8 PSEUDO!",
|
||||
[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
|
||||
imm:$cond, EFLAGS))]>;
|
||||
|
||||
let Predicates = [NoCMov] in {
|
||||
def CMOV_GR32 : I<0, Pseudo,
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
|
||||
"#CMOV_GR32* PSEUDO!",
|
||||
[(set GR32:$dst,
|
||||
(X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
|
||||
def CMOV_GR16 : I<0, Pseudo,
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
|
||||
"#CMOV_GR16* PSEUDO!",
|
||||
[(set GR16:$dst,
|
||||
(X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
|
||||
def CMOV_RFP32 : I<0, Pseudo,
|
||||
(outs RFP32:$dst),
|
||||
(ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
|
||||
"#CMOV_RFP32 PSEUDO!",
|
||||
[(set RFP32:$dst,
|
||||
(X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def CMOV_RFP64 : I<0, Pseudo,
|
||||
(outs RFP64:$dst),
|
||||
(ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
|
||||
"#CMOV_RFP64 PSEUDO!",
|
||||
[(set RFP64:$dst,
|
||||
(X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def CMOV_RFP80 : I<0, Pseudo,
|
||||
(outs RFP80:$dst),
|
||||
(ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
|
||||
"#CMOV_RFP80 PSEUDO!",
|
||||
[(set RFP80:$dst,
|
||||
(X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
} // Predicates = [NoCMov]
|
||||
} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
|
||||
} // Uses = [EFLAGS]
|
||||
|
||||
} // Constraints = "$src1 = $dst" in
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Atomic Instruction Pseudo Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
Loading…
Reference in New Issue
Block a user