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https://github.com/c64scene-ar/llvm-6502.git
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Add the "unpack low packed data" instructions. This should be the last of
the MMX instructions that are needed... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
2ad28e6c48
commit
6dc29ece6e
@ -2,8 +2,8 @@
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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// This file was developed by the Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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@ -128,6 +128,8 @@ def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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// -- Addition
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defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
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defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
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defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
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@ -138,6 +140,7 @@ defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
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defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
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defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
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// -- Subtraction
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defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
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defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
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defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
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@ -148,67 +151,13 @@ defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
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defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
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defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
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// -- Multiplication
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defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
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// -- Multiply and Add
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
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// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
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// MMX_PSHUF*, MMX_SHUFP* etc. imm.
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def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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def MMX_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}], MMX_SHUFFLE_get_shuf_imm>;
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def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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let isTwoAddress = 1 in {
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def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1,
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(bc_v8i8 (load_mmx addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1,
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(bc_v4i16 (load_mmx addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v1i64 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v1i64 (vector_shuffle VR64:$src1,
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(load_mmx addr:$src2),
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MMX_UNPCKH_shuffle_mask)))]>;
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}
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
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defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
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@ -247,12 +196,7 @@ defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
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defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_mmx_psra_d>;
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// Pack instructions
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defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
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// Integer comparison
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// Comparison Instructions
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defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
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defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
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defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
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@ -261,7 +205,110 @@ defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
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defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
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defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
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// Move Instructions
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// Conversion Instructions
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def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKLMask(N);
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}]>;
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// -- Unpack Instructions
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let isTwoAddress = 1 in {
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// Unpack High Packed Data Instructions
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def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1,
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(bc_v8i8 (load_mmx addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1,
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(bc_v4i16 (load_mmx addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle VR64:$src1,
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(bc_v2i32 (load_mmx addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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// Unpack Low Packed Data Instructions
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def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpcklbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKL_shuffle_mask)))]>;
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def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpcklbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1,
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(bc_v8i8 (load_mmx addr:$src2)),
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MMX_UNPCKL_shuffle_mask)))]>;
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def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpcklwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKL_shuffle_mask)))]>;
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def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpcklwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1,
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(bc_v4i16 (load_mmx addr:$src2)),
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MMX_UNPCKL_shuffle_mask)))]>;
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def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckldq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKL_shuffle_mask)))]>;
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def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckldq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle VR64:$src1,
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(bc_v2i32 (load_mmx addr:$src2)),
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MMX_UNPCKL_shuffle_mask)))]>;
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}
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// -- Pack Instructions
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defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
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// Data Transfer Instructions
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def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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def MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
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@ -326,12 +373,12 @@ def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
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// Alias instructions that map zero vector to pxor.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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let isReMaterializable = 1 in {
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def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
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"pxor $dst, $dst",
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[(set VR64:$dst, (v1i64 immAllZerosV))]>;
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def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
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"pcmpeqd $dst, $dst",
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[(set VR64:$dst, (v1i64 immAllOnesV))]>;
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def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
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"pxor $dst, $dst",
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[(set VR64:$dst, (v1i64 immAllZerosV))]>;
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def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
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"pcmpeqd $dst, $dst",
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[(set VR64:$dst, (v1i64 immAllOnesV))]>;
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}
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//===----------------------------------------------------------------------===//
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@ -373,6 +420,16 @@ def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
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def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
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// Splat v1i64
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// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
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// MMX_PSHUF*, MMX_SHUFP* etc. imm.
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def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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def MMX_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}], MMX_SHUFFLE_get_shuf_imm>;
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let AddedComplexity = 10 in {
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def : Pat<(vector_shuffle (v1i64 VR64:$src), (undef),
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MMX_splat_mask:$sm),
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@ -389,7 +446,7 @@ def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
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def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
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def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
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// Some special case pandn patterns.
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// Some special case PANDN patterns.
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def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
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VR64:$src2)),
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(MMX_PANDNrr VR64:$src1, VR64:$src2)>;
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