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Move ScheduleDAGInstrs.h to be a private header. Front-ends
that used this header to select a scheduling policy should use SchedulerRegistry.h instead (llvm-gcc and clang were updated a while ago). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -19,8 +19,8 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "post-RA-sched"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/MachineDominators.h"
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@@ -13,12 +13,12 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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82
lib/CodeGen/ScheduleDAGInstrs.h
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82
lib/CodeGen/ScheduleDAGInstrs.h
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@@ -0,0 +1,82 @@
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//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGInstrs class, which implements
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// scheduling for a MachineInstr-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SCHEDULEDAGINSTRS_H
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#define SCHEDULEDAGINSTRS_H
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class MachineLoopInfo;
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class MachineDominatorTree;
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class ScheduleDAGInstrs : public ScheduleDAG {
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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/// Defs, Uses - Remember where defs and uses of each physical register
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/// are as we iterate upward through the instructions. This is allocated
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/// here instead of inside BuildSchedGraph to avoid the need for it to be
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/// initialized and destructed for each block.
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std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister];
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std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister];
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/// PendingLoads - Remember where unknown loads are after the most recent
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/// unknown store, as we iterate. As with Defs and Uses, this is here
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/// to minimize construction/destruction.
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std::vector<SUnit *> PendingLoads;
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public:
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt);
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virtual ~ScheduleDAGInstrs() {}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(MachineInstr *MI) {
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#ifndef NDEBUG
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const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
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#endif
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SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
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/// input.
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virtual void BuildSchedGraph();
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/// ComputeLatency - Compute node latency.
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///
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virtual void ComputeLatency(SUnit *SU);
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virtual MachineBasicBlock *EmitSchedule();
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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virtual void dumpNode(const SUnit *SU) const;
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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};
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}
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#endif
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