From 6dd98a6c317404b3b700573e6b3a7b627ba38ff4 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 4 Feb 2002 00:33:08 +0000 Subject: [PATCH] Split RegisterAllocation stuff OUT of Sparc.cpp into a well defined pass that has a very minimal interface (like it should have). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1667 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RegisterAllocation.h | 24 +++++++++++++++++ lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | 19 ++++++++++++-- lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp | 19 ++++++++++++-- lib/Target/SparcV9/SparcV9TargetMachine.cpp | 29 ++------------------- 4 files changed, 60 insertions(+), 31 deletions(-) create mode 100644 include/llvm/CodeGen/RegisterAllocation.h diff --git a/include/llvm/CodeGen/RegisterAllocation.h b/include/llvm/CodeGen/RegisterAllocation.h new file mode 100644 index 00000000000..161be18498b --- /dev/null +++ b/include/llvm/CodeGen/RegisterAllocation.h @@ -0,0 +1,24 @@ +//===-- CodeGen/RegisterAllocation.h - RegAlloc Pass -------------*- C++ -*--=// +// +// This pass register allocates a module, a method at a time. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_REGISTERALLOCATION_H +#define LLVM_CODEGEN_REGISTERALLOCATION_H + +#include "llvm/Pass.h" +class TargetMachine; + +//---------------------------------------------------------------------------- +// Entry point for register allocation for a module +//---------------------------------------------------------------------------- + +class RegisterAllocation : public MethodPass { + TargetMachine &Target; +public: + inline RegisterAllocation(TargetMachine &T) : Target(T) {} + bool runOnMethod(Method *M); +}; + +#endif diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index 61a20198118..6ba63e3051d 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -10,6 +10,7 @@ // 9/10/01 - Ruchira Sasanka - created. //**************************************************************************/ +#include "llvm/CodeGen/RegisterAllocation.h" #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineCodeForMethod.h" @@ -23,8 +24,6 @@ using std::cerr; // ***TODO: There are several places we add instructions. Validate the order // of adding these instructions. - - cl::Enum DEBUG_RA("dregalloc", cl::NoFlags, "enable register allocation debugging information", clEnumValN(RA_DEBUG_None , "n", "disable debug output"), @@ -32,6 +31,22 @@ cl::Enum DEBUG_RA("dregalloc", cl::NoFlags, clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0); +bool RegisterAllocation::runOnMethod(Method *M) { + if (DEBUG_RA) + cerr << "\n******************** Method "<< M->getName() + << " ********************\n"; + + MethodLiveVarInfo LVI(M ); // Analyze live varaibles + LVI.analyze(); + + PhyRegAlloc PRA(M, Target, &LVI); // allocate registers + PRA.allocateRegisters(); + + if (DEBUG_RA) cerr << "\nRegister allocation complete!\n"; + return false; +} + + //---------------------------------------------------------------------------- // Constructor: Init local composite objects and create register classes. //---------------------------------------------------------------------------- diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 61a20198118..6ba63e3051d 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -10,6 +10,7 @@ // 9/10/01 - Ruchira Sasanka - created. //**************************************************************************/ +#include "llvm/CodeGen/RegisterAllocation.h" #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineCodeForMethod.h" @@ -23,8 +24,6 @@ using std::cerr; // ***TODO: There are several places we add instructions. Validate the order // of adding these instructions. - - cl::Enum DEBUG_RA("dregalloc", cl::NoFlags, "enable register allocation debugging information", clEnumValN(RA_DEBUG_None , "n", "disable debug output"), @@ -32,6 +31,22 @@ cl::Enum DEBUG_RA("dregalloc", cl::NoFlags, clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0); +bool RegisterAllocation::runOnMethod(Method *M) { + if (DEBUG_RA) + cerr << "\n******************** Method "<< M->getName() + << " ********************\n"; + + MethodLiveVarInfo LVI(M ); // Analyze live varaibles + LVI.analyze(); + + PhyRegAlloc PRA(M, Target, &LVI); // allocate registers + PRA.allocateRegisters(); + + if (DEBUG_RA) cerr << "\nRegister allocation complete!\n"; + return false; +} + + //---------------------------------------------------------------------------- // Constructor: Init local composite objects and create register classes. //---------------------------------------------------------------------------- diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp index 2476a5f574a..8ca947ae297 100644 --- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp +++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp @@ -16,7 +16,7 @@ #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForMethod.h" -#include "llvm/CodeGen/PhyRegAlloc.h" +#include "llvm/CodeGen/RegisterAllocation.h" #include "llvm/Method.h" #include "llvm/PassManager.h" #include @@ -40,32 +40,6 @@ const MachineInstrDescriptor SparcMachineInstrDesc[] = { TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); } -//---------------------------------------------------------------------------- -// Entry point for register allocation for a module -//---------------------------------------------------------------------------- - -class RegisterAllocation : public MethodPass { - TargetMachine &Target; -public: - inline RegisterAllocation(TargetMachine &T) : Target(T) {} - bool runOnMethod(Method *M) { - if (DEBUG_RA) - cerr << "\n******************** Method "<< M->getName() - << " ********************\n"; - - MethodLiveVarInfo LVI(M ); // Analyze live varaibles - LVI.analyze(); - - PhyRegAlloc PRA(M, Target, &LVI); // allocate registers - PRA.allocateRegisters(); - - if (DEBUG_RA) cerr << "\nRegister allocation complete!\n"; - return false; - } -}; - -static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR]; - //--------------------------------------------------------------------------- // class InsertPrologEpilogCode // @@ -77,6 +51,7 @@ static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR]; // with the leaf method optimization. // //--------------------------------------------------------------------------- +static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR]; class InsertPrologEpilogCode : public MethodPass { TargetMachine &Target;