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fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
to be folded into non-store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35601 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1332,6 +1332,15 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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// r + r
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if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
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return true;
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case MVT::isVoid:
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// Note, we allow "void" uses (basically, uses that aren't loads or
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// stores), because arm allows folding a scale into many arithmetic
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// operations. This should be made more precise and revisited later.
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// Allow r << imm, but the imm has to be a multiple of two.
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if (AM.Scale & 1) return false;
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return isPowerOf2_32(AM.Scale);
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}
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break;
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}
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@ -1413,12 +1422,19 @@ bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
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case MVT::i1:
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case MVT::i8:
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case MVT::i32:
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// r + r
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if (S == 2)
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return true;
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// r + r << imm
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// Allow: r + r
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// Allow: r << imm
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// Allow: r + r << imm
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S &= ~1;
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return isPowerOf2_32(S);
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case MVT::isVoid:
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// Note, we allow "void" uses (basically, uses that aren't loads or
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// stores), because arm allows folding a scale into many arithmetic
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// operations. This should be made more precise and revisited later.
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// Allow r << imm, but the imm has to be a multiple of two.
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if (S & 1) return false;
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return isPowerOf2_32(S);
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}
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}
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