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fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales

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to be folded into non-store instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35601 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-04-02 18:51:18 +00:00
parent bcfd4665b5
commit 6e0784da77
1 changed files with 20 additions and 4 deletions
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24
lib/Target/ARM/ARMISelLowering.cpp
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@ -1332,6 +1332,15 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
// r + r
if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
return true;
case MVT::isVoid:
// Note, we allow "void" uses (basically, uses that aren't loads or
// stores), because arm allows folding a scale into many arithmetic
// operations. This should be made more precise and revisited later.
// Allow r << imm, but the imm has to be a multiple of two.
if (AM.Scale & 1) return false;
return isPowerOf2_32(AM.Scale);
}
break;
}
@ -1413,12 +1422,19 @@ bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
case MVT::i1:
case MVT::i8:
case MVT::i32:
// r + r
if (S == 2)
return true;
// r + r << imm
// Allow: r + r
// Allow: r << imm
// Allow: r + r << imm
S &= ~1;
return isPowerOf2_32(S);
case MVT::isVoid:
// Note, we allow "void" uses (basically, uses that aren't loads or
// stores), because arm allows folding a scale into many arithmetic
// operations. This should be made more precise and revisited later.
// Allow r << imm, but the imm has to be a multiple of two.
if (S & 1) return false;
return isPowerOf2_32(S);
}
}