6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-19 03:24:09 +00:00
Code Issues Projects Releases Wiki Activity

s/ARM::BRIND/ARM::BX/g to coincide with r120366.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2010-11-30 00:48:15 +00:00
parent 13815d9d3e
commit 6e46d84eea
3 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -790,7 +790,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Misc. Branch Instructions.
// BLXr9, BXr9
// BRIND, BX_RET
// BX, BX_RET
static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@ -805,8 +805,8 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
if (Opcode == ARM::BX_RET)
return true;
// BLXr9 and BRIND take one GPR reg.
if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
// BLXr9 and BX take one GPR reg.
if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) {
assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,