mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael J. Spencer
parent
01aabdac44
commit
6e56b18e57
@ -76,7 +76,7 @@ namespace llvm {
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///
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CALL,
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/// RDTSC_DAG - This operation implements the lowering for
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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@ -171,14 +171,14 @@ namespace llvm {
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// TLSADDR - Thread Local Storage.
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TLSADDR,
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// TLSCALL - Thread Local Storage. When calling to an OS provided
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// thunk at the address from an earlier relocation.
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TLSCALL,
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// EH_RETURN - Exception Handling helpers.
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EH_RETURN,
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/// TC_RETURN - Tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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@ -195,7 +195,7 @@ namespace llvm {
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// CMPPD, CMPPS - Vector double/float comparison.
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// CMPPD, CMPPS - Vector double/float comparison.
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CMPPD, CMPPS,
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// PCMP* - Vector integer comparisons.
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PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
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PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
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@ -206,7 +206,7 @@ namespace llvm {
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// MUL_IMM - X86 specific multiply by immediate.
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MUL_IMM,
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// PTEST - Vector bitwise comparisons
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PTEST,
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@ -256,8 +256,8 @@ namespace llvm {
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// MINGW_ALLOCA - MingW's __alloca call to do stack probing.
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MINGW_ALLOCA,
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// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
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// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
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// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
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// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
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// Atomic 64-bit binary operations.
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ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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ATOMSUB64_DAG,
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@ -266,23 +266,23 @@ namespace llvm {
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ATOMAND64_DAG,
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ATOMNAND64_DAG,
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ATOMSWAP64_DAG,
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// Memory barrier
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MEMBARRIER,
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MFENCE,
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SFENCE,
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LFENCE,
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// LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
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LCMPXCHG_DAG,
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LCMPXCHG8_DAG,
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// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
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VZEXT_LOAD,
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// FNSTCW16m - Store FP control world into i16 memory.
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FNSTCW16m,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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@ -291,7 +291,7 @@ namespace llvm {
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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@ -299,13 +299,13 @@ namespace llvm {
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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@ -315,7 +315,7 @@ namespace llvm {
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/// VAARG_64 - This instruction grabs the address of the next argument
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/// from a va_list. (reads and modifies the va_list in memory)
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VAARG_64
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// WARNING: Do not add anything in the end unless you want the node to
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// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
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// thought as target memory ops!
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@ -432,14 +432,14 @@ namespace llvm {
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/// getPICBaseSymbol - Return the X86-32 PIC base.
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MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
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virtual unsigned getJumpTableEncoding() const;
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virtual const MCExpr *
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LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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const MachineBasicBlock *MBB, unsigned uid,
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MCContext &Ctx) const;
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/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
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/// jumptable.
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virtual SDValue getPICJumpTableRelocBase(SDValue Table,
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@ -447,7 +447,7 @@ namespace llvm {
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virtual const MCExpr *
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getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
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unsigned JTI, MCContext &Ctx) const;
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/// getStackPtrReg - Return the stack pointer register we are using: either
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/// ESP or RSP.
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unsigned getStackPtrReg() const { return X86StackPtr; }
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@ -491,7 +491,7 @@ namespace llvm {
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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/// isTypeDesirableForOp - Return true if the target has native support for
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@ -510,7 +510,7 @@ namespace llvm {
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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@ -518,12 +518,12 @@ namespace llvm {
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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@ -535,20 +535,20 @@ namespace llvm {
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virtual bool
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isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
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SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
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virtual bool ExpandInlineAsm(CallInst *CI) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value,
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/// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
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/// The operand object must already have been set up with the operand type.
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virtual int getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::vector<unsigned>
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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@ -562,15 +562,15 @@ namespace llvm {
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char ConstraintLetter,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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/// getRegForInlineAsmConstraint - Given a physical register constraint
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/// (e.g. {edx}), return the register number and the register class for the
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/// register. This should only be used for C_Register constraints. On
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/// error, this returns a register number of 0.
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std::pair<unsigned, const TargetRegisterClass*>
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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@ -625,7 +625,7 @@ namespace llvm {
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// shrink long double fp constant since fldt is very slow.
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return !X86ScalarSSEf64 || VT == MVT::f80;
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}
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const X86Subtarget* getSubtarget() const {
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return Subtarget;
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}
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@ -666,8 +666,8 @@ namespace llvm {
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/// X86StackPtr - X86 physical register used as stack ptr.
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unsigned X86StackPtr;
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/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
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/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
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/// floating point ops.
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/// When SSE is available, use it for f32 operations.
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/// When SSE2 is available, use it for f64 operations.
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@ -849,7 +849,7 @@ namespace llvm {
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unsigned immOpcL,
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unsigned immOpcH,
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bool invSrc = false) const;
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/// Utility function to emit atomic min and max. It takes the min/max
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/// instruction to expand, the associated basic block, and the associated
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/// cmov opcode for moving the min or max value.
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@ -872,7 +872,7 @@ namespace llvm {
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MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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@ -1,10 +1,10 @@
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//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the various pseudo instructions used by the compiler,
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@ -149,7 +149,7 @@ def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"",
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[(set GR16:$dst, 0)]>, OpSize;
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// FIXME: Set encoding to pseudo.
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, 0)]>;
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@ -196,7 +196,7 @@ def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
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def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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(SETB_C64r)>;
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//===----------------------------------------------------------------------===//
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// String Pseudo Instructions
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//
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@ -212,7 +212,7 @@ def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
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let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
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def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
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[(X86rep_movs i64)]>, REP;
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// FIXME: Should use "(X86rep_stos AL)" as the pattern.
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let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
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@ -268,8 +268,8 @@ def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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Requires<[In64BitMode]>;
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// Darwin TLS Support
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// For i386, the address of the thunk is passed on the stack, on return the
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// address of the variable is in %eax. %ecx is trashed during the function
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// For i386, the address of the thunk is passed on the stack, on return the
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// address of the variable is in %eax. %ecx is trashed during the function
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// call. All other registers are preserved.
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let Defs = [EAX, ECX],
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Uses = [ESP],
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@ -279,7 +279,7 @@ def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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[(X86TLSCall addr:$sym)]>,
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Requires<[In32BitMode]>;
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// For x86_64, the address of the thunk is passed in %rdi, on return
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// For x86_64, the address of the thunk is passed in %rdi, on return
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// the address of the variable is in %rax. All other registers are preserved.
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let Defs = [RAX],
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Uses = [RDI],
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@ -344,7 +344,7 @@ def CMOV_RFP80 : I<0, Pseudo,
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(X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
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EFLAGS))]>;
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} // Predicates = [NoCMov]
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} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
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} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
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} // Uses = [EFLAGS]
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} // Constraints = "$src1 = $dst" in
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@ -357,100 +357,100 @@ def CMOV_RFP80 : I<0, Pseudo,
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// Atomic exchange, and, or, xor
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let Constraints = "$val = $dst", Defs = [EFLAGS],
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usesCustomInserter = 1 in {
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def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMAND8 PSEUDO!",
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"#ATOMAND8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
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def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMOR8 PSEUDO!",
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"#ATOMOR8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
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def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMXOR8 PSEUDO!",
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"#ATOMXOR8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
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def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMNAND8 PSEUDO!",
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"#ATOMNAND8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
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def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMAND16 PSEUDO!",
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"#ATOMAND16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
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def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMOR16 PSEUDO!",
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"#ATOMOR16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
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def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMXOR16 PSEUDO!",
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"#ATOMXOR16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
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def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMNAND16 PSEUDO!",
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"#ATOMNAND16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
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def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
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"#ATOMMIN16 PSEUDO!",
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"#ATOMMIN16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
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def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMMAX16 PSEUDO!",
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"#ATOMMAX16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
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def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMUMIN16 PSEUDO!",
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"#ATOMUMIN16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
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def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMUMAX16 PSEUDO!",
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"#ATOMUMAX16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
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def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMAND32 PSEUDO!",
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"#ATOMAND32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
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def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMOR32 PSEUDO!",
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"#ATOMOR32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
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def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMXOR32 PSEUDO!",
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"#ATOMXOR32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
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def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMNAND32 PSEUDO!",
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"#ATOMNAND32 PSEUDO!",
|
||||
[(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
|
||||
def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
|
||||
"#ATOMMIN32 PSEUDO!",
|
||||
"#ATOMMIN32 PSEUDO!",
|
||||
[(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
|
||||
def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
||||
"#ATOMMAX32 PSEUDO!",
|
||||
"#ATOMMAX32 PSEUDO!",
|
||||
[(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
|
||||
def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
||||
"#ATOMUMIN32 PSEUDO!",
|
||||
"#ATOMUMIN32 PSEUDO!",
|
||||
[(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
|
||||
def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
||||
"#ATOMUMAX32 PSEUDO!",
|
||||
"#ATOMUMAX32 PSEUDO!",
|
||||
[(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
|
||||
|
||||
|
||||
|
||||
|
||||
def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMAND64 PSEUDO!",
|
||||
"#ATOMAND64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMOR64 PSEUDO!",
|
||||
"#ATOMOR64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMXOR64 PSEUDO!",
|
||||
"#ATOMXOR64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMNAND64 PSEUDO!",
|
||||
"#ATOMNAND64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMMIN64 PSEUDO!",
|
||||
"#ATOMMIN64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMMAX64 PSEUDO!",
|
||||
"#ATOMMAX64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMUMIN64 PSEUDO!",
|
||||
"#ATOMUMIN64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
|
||||
def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
||||
"#ATOMUMAX64 PSEUDO!",
|
||||
"#ATOMUMAX64 PSEUDO!",
|
||||
[(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
|
||||
}
|
||||
|
||||
let Constraints = "$val1 = $dst1, $val2 = $dst2",
|
||||
let Constraints = "$val1 = $dst1, $val2 = $dst2",
|
||||
Defs = [EFLAGS, EAX, EBX, ECX, EDX],
|
||||
Uses = [EAX, EBX, ECX, EDX],
|
||||
mayLoad = 1, mayStore = 1,
|
||||
@ -486,7 +486,7 @@ def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
||||
|
||||
// Memory barriers
|
||||
|
||||
// TODO: Get this to fold the constant into the instruction.
|
||||
// TODO: Get this to fold the constant into the instruction.
|
||||
def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
|
||||
"lock\n\t"
|
||||
"or{l}\t{$zero, $dst|$dst, $zero}",
|
||||
@ -497,7 +497,7 @@ def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
|
||||
"#MEMBARRIER",
|
||||
[(X86MemBarrier)]>, Requires<[HasSSE2]>;
|
||||
|
||||
// TODO: Get this to fold the constant into the instruction.
|
||||
// TODO: Get this to fold the constant into the instruction.
|
||||
let hasSideEffects = 1, Defs = [ESP] in
|
||||
def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
|
||||
"lock\n\t"
|
||||
@ -520,7 +520,7 @@ def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
"lock\n\t"
|
||||
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
|
||||
|
||||
def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
|
||||
"lock\n\t"
|
||||
"add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
@ -552,21 +552,21 @@ def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
|
||||
def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
"lock\n\t"
|
||||
"sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
||||
def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
"lock\n\t"
|
||||
"sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
"lock\n\t"
|
||||
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
|
||||
|
||||
def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
|
||||
def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
|
||||
"lock\n\t"
|
||||
"sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
||||
def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
||||
"lock\n\t"
|
||||
"sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
||||
def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
||||
def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
||||
"lock\n\t"
|
||||
"sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
|
||||
@ -582,7 +582,7 @@ def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
||||
"lock\n\t"
|
||||
"sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
|
||||
(ins i64mem:$dst, i64i8imm :$src2),
|
||||
(ins i64mem:$dst, i64i8imm :$src2),
|
||||
"lock\n\t"
|
||||
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
||||
|
||||
@ -838,7 +838,7 @@ def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
// FIXME: This is disabled for 32-bit PIC mode because the global base
|
||||
// register which is part of the address mode may be assigned a
|
||||
// register which is part of the address mode may be assigned a
|
||||
// callee-saved register.
|
||||
def : Pat<(X86tcret (load addr:$dst), imm:$off),
|
||||
(TCRETURNmi addr:$dst, imm:$off)>,
|
||||
@ -961,8 +961,8 @@ def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
|
||||
def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
|
||||
|
||||
// extload bool -> extload byte
|
||||
// When extloading from 16-bit and smaller memory locations into 64-bit
|
||||
// registers, use zero-extending loads so that the entire 64-bit register is
|
||||
// When extloading from 16-bit and smaller memory locations into 64-bit
|
||||
// registers, use zero-extending loads so that the entire 64-bit register is
|
||||
// defined, avoiding partial-register updates.
|
||||
|
||||
def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
|
||||
@ -1142,13 +1142,13 @@ def : Pat<(and GR32:$src1, 0xffff),
|
||||
(MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
|
||||
// r & (2^8-1) ==> movz
|
||||
def : Pat<(and GR32:$src1, 0xff),
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
|
||||
GR32_ABCD)),
|
||||
sub_8bit))>,
|
||||
Requires<[In32BitMode]>;
|
||||
// r & (2^8-1) ==> movz
|
||||
def : Pat<(and GR16:$src1, 0xff),
|
||||
(MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
|
||||
(MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
|
||||
GR16_ABCD)),
|
||||
sub_8bit))>,
|
||||
Requires<[In32BitMode]>;
|
||||
@ -1176,12 +1176,12 @@ def : Pat<(and GR16:$src1, 0xff),
|
||||
def : Pat<(sext_inreg GR32:$src, i16),
|
||||
(MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
|
||||
def : Pat<(sext_inreg GR32:$src, i8),
|
||||
(MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
(MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
GR32_ABCD)),
|
||||
sub_8bit))>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(sext_inreg GR16:$src, i8),
|
||||
(MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
||||
(MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
||||
GR16_ABCD)),
|
||||
sub_8bit))>,
|
||||
Requires<[In32BitMode]>;
|
||||
@ -1241,26 +1241,26 @@ def : Pat<(srl GR16:$src, (i8 8)),
|
||||
sub_16bit)>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
||||
GR16_ABCD)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
||||
GR16_ABCD)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
GR32_ABCD)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
GR32_ABCD)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
|
||||
// h-register tricks.
|
||||
// For now, be conservative on x86-64 and use an h-register extract only if the
|
||||
// value is immediately zero-extended or stored, which are somewhat common
|
||||
@ -1282,7 +1282,7 @@ def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In64BitMode]>;
|
||||
def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
|
||||
(MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
(MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
||||
GR32_ABCD)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In64BitMode]>;
|
||||
@ -1336,8 +1336,8 @@ def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
|
||||
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
||||
sub_8bit_hi))>,
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
|
||||
|
||||
|
||||
// (shl x, 1) ==> (add x, x)
|
||||
def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
|
||||
def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
//===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the X86 instruction set, defining the instructions, and
|
||||
@ -46,7 +46,7 @@ def SDTX86SetCC_C : SDTypeProfile<1, 2,
|
||||
[SDTCisInt<0>,
|
||||
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
|
||||
|
||||
def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
|
||||
def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
|
||||
SDTCisVT<2, i8>]>;
|
||||
def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
|
||||
|
||||
@ -120,25 +120,25 @@ def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
|
||||
[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
[SDNPHasChain, SDNPMayStore,
|
||||
SDNPMayLoad, SDNPMemOperand]>;
|
||||
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
|
||||
[SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
|
||||
@ -156,7 +156,7 @@ def X86callseq_start :
|
||||
[SDNPHasChain, SDNPOutFlag]>;
|
||||
def X86callseq_end :
|
||||
SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
|
||||
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
|
||||
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
|
||||
|
||||
def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
|
||||
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
|
||||
@ -180,7 +180,7 @@ def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
|
||||
def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
|
||||
[SDNPHasChain]>;
|
||||
|
||||
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
|
||||
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
|
||||
[SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
|
||||
|
||||
def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
|
||||
@ -190,7 +190,7 @@ def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
|
||||
[SDNPCommutative]>;
|
||||
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
|
||||
[SDNPCommutative]>;
|
||||
|
||||
|
||||
def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
|
||||
def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
|
||||
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
|
||||
@ -616,13 +616,13 @@ def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
|
||||
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
|
||||
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
|
||||
|
||||
def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
|
||||
def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
|
||||
"push{l}\t$imm", []>;
|
||||
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
||||
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
||||
"push{w}\t$imm", []>, OpSize;
|
||||
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
|
||||
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
|
||||
"push{l}\t$imm", []>;
|
||||
|
||||
|
||||
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
|
||||
def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
|
||||
Requires<[In32BitMode]>;
|
||||
@ -646,9 +646,9 @@ def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
|
||||
}
|
||||
|
||||
let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
|
||||
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
|
||||
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
|
||||
"push{q}\t$imm", []>;
|
||||
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
||||
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
||||
"push{q}\t$imm", []>;
|
||||
def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
|
||||
"push{q}\t$imm", []>;
|
||||
@ -677,11 +677,11 @@ def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
|
||||
let Constraints = "$src = $dst" in { // GR32 = bswap GR32
|
||||
def BSWAP32r : I<0xC8, AddRegFrm,
|
||||
(outs GR32:$dst), (ins GR32:$src),
|
||||
"bswap{l}\t$dst",
|
||||
"bswap{l}\t$dst",
|
||||
[(set GR32:$dst, (bswap GR32:$src))]>, TB;
|
||||
|
||||
|
||||
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
|
||||
"bswap{q}\t$dst",
|
||||
"bswap{q}\t$dst",
|
||||
[(set GR64:$dst, (bswap GR64:$src))]>, TB;
|
||||
} // Constraints = "$src = $dst"
|
||||
|
||||
@ -823,7 +823,7 @@ def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
|
||||
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
|
||||
"mov{l}\t{%eax, $dst|$dst, %eax}", []>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
|
||||
// FIXME: These definitions are utterly broken
|
||||
// Just leave them commented out for now because they're useless outside
|
||||
// of the large code model, and most compilers won't generate the instructions
|
||||
@ -926,13 +926,13 @@ def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
// only for now.
|
||||
|
||||
def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
||||
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
||||
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
||||
// [(X86bt (loadi16 addr:$src1), GR16:$src2),
|
||||
// (implicit EFLAGS)]
|
||||
[]
|
||||
>, OpSize, TB, Requires<[FastBTMem]>;
|
||||
def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
||||
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
||||
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
||||
// [(X86bt (loadi32 addr:$src1), GR32:$src2),
|
||||
// (implicit EFLAGS)]
|
||||
[]
|
||||
@ -1058,20 +1058,20 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
// operand is referenced, the atomicity is ensured.
|
||||
let Constraints = "$val = $dst" in {
|
||||
def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
||||
"xchg{b}\t{$val, $ptr|$ptr, $val}",
|
||||
"xchg{b}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
|
||||
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
|
||||
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
|
||||
(ins GR16:$val, i16mem:$ptr),
|
||||
"xchg{w}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
|
||||
"xchg{w}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
|
||||
OpSize;
|
||||
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
|
||||
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$val, i32mem:$ptr),
|
||||
"xchg{l}\t{$val, $ptr|$ptr, $val}",
|
||||
"xchg{l}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
|
||||
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
|
||||
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$val,i64mem:$ptr),
|
||||
"xchg{q}\t{$val, $ptr|$ptr, $val}",
|
||||
"xchg{q}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
|
||||
|
||||
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
|
||||
@ -1196,7 +1196,7 @@ def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
|
||||
def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
|
||||
"aam\t$src", []>, Requires<[In32BitMode]>;
|
||||
|
||||
// ASCII Adjust AL After Subtraction - sets
|
||||
// ASCII Adjust AL After Subtraction - sets
|
||||
// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
|
||||
def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
|
||||
|
||||
@ -1211,16 +1211,16 @@ def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
|
||||
// Check Array Index Against Bounds
|
||||
def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"bound\t{$src, $dst|$dst, $src}", []>, OpSize,
|
||||
Requires<[In32BitMode]>;
|
||||
Requires<[In32BitMode]>;
|
||||
def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"bound\t{$src, $dst|$dst, $src}", []>,
|
||||
Requires<[In32BitMode]>;
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
// Adjust RPL Field of Segment Selector
|
||||
def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
|
||||
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
|
||||
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
|
||||
def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
|
||||
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
|
||||
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subsystems.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user