6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Fix assertion on sign extend of 3 vectors

Browse Source 
This was trying to create an MVT with 3x vectors which
created an invalid EVT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222942 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-11-28 22:51:38 +00:00
parent 5f95140d02
commit 6e5862cb8c
2 changed files with 49 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/R600/SIISelLowering.cpp
View File

@ -640,11 +640,11 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
return BB;
}
EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
EVT SITargetLowering::getSetCCResultType(LLVMContext &Ctx, EVT VT) const {
if (!VT.isVector()) {
return MVT::i1;
}
return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
}
MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {

49
test/CodeGen/R600/setcc.ll
View File

@ -1,5 +1,7 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; FUNC-LABEL: {{^}}setcc_v2i32:
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
@ -343,3 +345,46 @@ entry:
store i32 %1, i32 addrspace(1)* %out
ret void
}
; FIXME: This does 4 compares
; FUNC-LABEL: {{^}}v3i32_eq:
; SI-DAG: v_cmp_eq_i32
; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
; SI-DAG: v_cmp_eq_i32
; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
; SI-DAG: v_cmp_eq_i32
; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
; SI: s_endpgm
define void @v3i32_eq(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %ptra, <3 x i32> addrspace(1)* %ptrb) {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep.a = getelementptr <3 x i32> addrspace(1)* %ptra, i32 %tid
%gep.b = getelementptr <3 x i32> addrspace(1)* %ptrb, i32 %tid
%gep.out = getelementptr <3 x i32> addrspace(1)* %out, i32 %tid
%a = load <3 x i32> addrspace(1)* %gep.a
%b = load <3 x i32> addrspace(1)* %gep.b
%cmp = icmp eq <3 x i32> %a, %b
%ext = sext <3 x i1> %cmp to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %gep.out
ret void
}
; FUNC-LABEL: {{^}}v3i8_eq:
; SI-DAG: v_cmp_eq_i32
; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
; SI-DAG: v_cmp_eq_i32
; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
; SI-DAG: v_cmp_eq_i32
; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
; SI: s_endpgm
define void @v3i8_eq(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %ptra, <3 x i8> addrspace(1)* %ptrb) {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep.a = getelementptr <3 x i8> addrspace(1)* %ptra, i32 %tid
%gep.b = getelementptr <3 x i8> addrspace(1)* %ptrb, i32 %tid
%gep.out = getelementptr <3 x i8> addrspace(1)* %out, i32 %tid
%a = load <3 x i8> addrspace(1)* %gep.a
%b = load <3 x i8> addrspace(1)* %gep.b
%cmp = icmp eq <3 x i8> %a, %b
%ext = sext <3 x i1> %cmp to <3 x i8>
store <3 x i8> %ext, <3 x i8> addrspace(1)* %gep.out
ret void
}