From 6e90ce21cc2b0627ee9219e3fb0cf808f2b73328 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Tue, 21 Dec 2010 02:12:07 +0000 Subject: [PATCH] If we're not using reg+reg offset we're using reg+imm, set the opcode to be the one we want to use. bugpoint reduced testcase is a little large, I'll see if I can simplify it down more. Fixes part of rdar://8782207 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122307 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Thumb1RegisterInfo.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 9f917234d13..07c12102798 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -656,7 +656,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, *this, dl); } - MI.setDesc(TII.get(ARM::tLDRr)); + MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) // Use [reg, reg] addrmode. @@ -676,7 +676,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } else emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII, *this, dl); - MI.setDesc(TII.get(ARM::tSTRr)); + MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi)); MI.getOperand(i).ChangeToRegister(VReg, false, false, true); if (UseRR) // Use [reg, reg] addrmode. MI.addOperand(MachineOperand::CreateReg(FrameReg, false));