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[arm fast-isel] Appease the machine verifier by using the proper register

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classes.  The vast majority of the remaining issues are due to uses of
invalid registers, which are defined by getRegForValue().  Those will be
a little more challenging to cleanup.
rdar://12719844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-11-27 22:29:43 +00:00
parent b1146a242c
commit 6e99a8cb37
1 changed files with 7 additions and 9 deletions
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16
lib/Target/ARM/ARMFastISel.cpp
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@ -2586,26 +2586,24 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
default: return 0;
case MVT::i16:
if (!Subtarget->hasV6Ops()) return 0;
if (isZExt) {
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
if (isZExt)
Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
} else {
else
Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
}
break;
case MVT::i8:
if (!Subtarget->hasV6Ops()) return 0;
if (isZExt) {
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
if (isZExt)
Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
} else {
else
Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
}
break;
case MVT::i1:
if (isZExt) {
Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
isBoolZext = true;
break;
}