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https://github.com/c64scene-ar/llvm-6502.git
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[Sparc] Implement spill and load for long double(f128) registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
195dd8a1ce
commit
6ee0857bd7
@ -44,7 +44,8 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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if (MI->getOpcode() == SP::LDri ||
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MI->getOpcode() == SP::LDXri ||
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MI->getOpcode() == SP::LDFri ||
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MI->getOpcode() == SP::LDDFri) {
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MI->getOpcode() == SP::LDDFri ||
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MI->getOpcode() == SP::LDQFri) {
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if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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@ -64,7 +65,8 @@ unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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if (MI->getOpcode() == SP::STri ||
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MI->getOpcode() == SP::STXri ||
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MI->getOpcode() == SP::STFri ||
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MI->getOpcode() == SP::STDFri) {
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MI->getOpcode() == SP::STDFri ||
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MI->getOpcode() == SP::STQFri) {
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if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
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MI->getOperand(1).getImm() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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@ -273,6 +275,16 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned numSubRegs = 0;
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unsigned movOpc = 0;
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const unsigned *subRegIdx = 0;
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const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
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const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
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const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
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SP::sub_odd64_then_sub_even,
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SP::sub_odd64_then_sub_odd };
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if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
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.addReg(SrcReg, getKillRegState(KillSrc));
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@ -285,23 +297,47 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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// Use two FMOVS instructions.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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MachineInstr *MovMI = 0;
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unsigned subRegIdx[] = {SP::sub_even, SP::sub_odd};
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for (unsigned i = 0; i != 2; ++i) {
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unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
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unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
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assert(Dst && Src && "Bad sub-register");
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MovMI = BuildMI(MBB, I, DL, get(SP::FMOVS), Dst).addReg(Src);
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subRegIdx = DFP_FP_SubRegsIdx;
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numSubRegs = 2;
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movOpc = SP::FMOVS;
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}
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} else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
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if (Subtarget.isV9()) {
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if (Subtarget.hasHardQuad()) {
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BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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// Use two FMOVD instructions.
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subRegIdx = QFP_DFP_SubRegsIdx;
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numSubRegs = 2;
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movOpc = SP::FMOVD;
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}
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// Add implicit super-register defs and kills to the last MovMI.
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MovMI->addRegisterDefined(DestReg, TRI);
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if (KillSrc)
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MovMI->addRegisterKilled(SrcReg, TRI);
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} else {
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// Use four FMOVS instructions.
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subRegIdx = QFP_FP_SubRegsIdx;
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numSubRegs = 4;
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movOpc = SP::FMOVS;
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}
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} else
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llvm_unreachable("Impossible reg-to-reg copy");
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if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0)
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return;
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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MachineInstr *MovMI = 0;
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for (unsigned i = 0; i != numSubRegs; ++i) {
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unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
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unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
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assert(Dst && Src && "Bad sub-register");
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MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
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}
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// Add implicit super-register defs and kills to the last MovMI.
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MovMI->addRegisterDefined(DestReg, TRI);
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if (KillSrc)
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MovMI->addRegisterKilled(SrcReg, TRI);
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}
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void SparcInstrInfo::
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@ -321,7 +357,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MFI.getObjectAlignment(FI));
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == &SP::I64RegsRegClass)
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if (RC == &SP::I64RegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (RC == &SP::IntRegsRegClass)
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@ -330,9 +366,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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else if (RC == &SP::FPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (RC == &SP::DFPRegsRegClass)
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else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
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BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
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// Use STQFri irrespective of its legality. If STQ is not legal, it will be
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// lowered into two STDs in eliminateFrameIndex.
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BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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@ -362,9 +403,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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else if (RC == &SP::FPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else if (RC == &SP::DFPRegsRegClass)
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else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
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BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
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// Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
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// lowered into two LDDs in eliminateFrameIndex.
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BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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@ -87,6 +87,35 @@ SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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}
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static void replaceFI(MachineFunction &MF,
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MachineBasicBlock::iterator II,
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MachineInstr &MI,
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DebugLoc dl,
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unsigned FIOperandNum, int Offset,
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unsigned FramePtr)
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{
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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void
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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@ -111,25 +140,37 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
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}
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
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if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
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if (MI.getOpcode() == SP::STQFri) {
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned SrcReg = MI.getOperand(2).getReg();
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unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
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unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
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.addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
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replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
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MI.setDesc(TII.get(SP::STDFri));
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MI.getOperand(2).setReg(SrcOddReg);
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Offset += 8;
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} else if (MI.getOpcode() == SP::LDQFri) {
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
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unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
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.addReg(FramePtr).addImm(0);
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replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
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MI.setDesc(TII.get(SP::LDDFri));
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MI.getOperand(0).setReg(DestOddReg);
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Offset += 8;
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}
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}
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replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
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}
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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@ -25,3 +25,18 @@ entry:
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store fp128 %7, fp128* %scalar.result, align 8
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ret void
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}
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; CHECK-LABEL: f128_spill
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; CHECK: std %f{{.+}}, [%[[S0:.+]]]
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; CHECK: std %f{{.+}}, [%[[S1:.+]]]
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; CHECK-DAG: ldd [%[[S0]]], %f{{.+}}
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; CHECK-DAG: ldd [%[[S1]]], %f{{.+}}
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; CHECK: jmp
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define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) {
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entry:
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%0 = load fp128* %a, align 8
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
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store fp128 %0, fp128* %scalar.result, align 8
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ret void
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}
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