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Final de-tabification.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-02-27 06:33:05 +00:00
parent e1b332a304
commit 6ef781f3ce
10 changed files with 136 additions and 138 deletions
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1
include/llvm/IntrinsicsCellSPU.td
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@ -239,5 +239,4 @@ let TargetPrefix = "spu" in {
def int_spu_si_dfma: v2f64_rr<"dfma">;
def int_spu_si_dfnms: v2f64_rr<"dfnms">;
def int_spu_si_dfms: v2f64_rr<"dfms">;
}

7
lib/Target/IA64/IA64RegisterInfo.td
View File

@ -419,7 +419,7 @@ def GR : RegisterClass<"IA64", [i64], 64,
r104, r105, r106, r107, r108, r109, r110, r111,
r112, r113, r114, r115, r116, r117, r118, r119,
r120, r121, r122, r123, r124, r125, r126, r127,
r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down)
r0, r1, r2, r5, r12, r13, r22, rp]> // last 16 are special (look down)
{
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
@ -436,10 +436,9 @@ def GR : RegisterClass<"IA64", [i64], 64,
GRClass::allocation_order_end(const MachineFunction &MF) const {
int numReservedRegs=8;// the 8 special registers r0,r1,r2,r5,r12,r13 etc
// we also can't allocate registers for use as locals if they're
// already required as 'out' registers
// we also can't allocate registers for use as locals if they're already
// required as 'out' registers
numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
return end()-numReservedRegs; // hide registers appropriately
}
}];