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Use getDebugLoc forwarder instead of getNode()->getDebugLoc.

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No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2009-02-07 19:59:05 +00:00
parent a56c037ce1
commit 6f38cb61a9
12 changed files with 79 additions and 79 deletions
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6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -352,7 +352,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
}
}
}
Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(),
Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
NVT, &Ops[0], Ops.size());
}
VT = NVT;
@ -893,7 +893,7 @@ SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
"Can't unroll a vector with multiple results!");
unsigned NE = VT.getVectorNumElements();
MVT EltVT = VT.getVectorElementType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Scalars;
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
@ -5001,7 +5001,7 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
// lower to a store then an indexed load.
SDValue Vec = Op.getOperand(0);
SDValue Idx = Op.getOperand(1);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT TVT = Vec.getValueType();
unsigned NumElems = TVT.getVectorNumElements();

14
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -854,13 +854,13 @@ void DAGTypeLegalizer::SetIgnoredNodeResult(SDNode* N) {
/// BitConvertToInteger - Convert to an integer of the same size.
SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, Op.getNode()->getDebugLoc(),
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
MVT::getIntegerVT(BitWidth), Op);
}
SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
MVT DestVT) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Create the stack frame object. Make sure it is aligned for both
// the source and destination types.
SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT);
@ -924,7 +924,7 @@ void DAGTypeLegalizer::GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT) {
SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
SDValue Index) {
DebugLoc dl = Index.getNode()->getDebugLoc();
DebugLoc dl = Index.getDebugLoc();
// Make sure the index type is big enough to compute in.
if (Index.getValueType().bitsGT(TLI.getPointerTy()))
Index = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Index);
@ -942,8 +942,8 @@ SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
/// JoinIntegers - Build an integer with low bits Lo and high bits Hi.
SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
// Arbitrarily use dlHi for result DebugLoc
DebugLoc dlHi = Hi.getNode()->getDebugLoc();
DebugLoc dlLo = Lo.getNode()->getDebugLoc();
DebugLoc dlHi = Hi.getDebugLoc();
DebugLoc dlLo = Lo.getDebugLoc();
MVT LVT = Lo.getValueType();
MVT HVT = Hi.getValueType();
MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
@ -1006,7 +1006,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
/// of the given type. A target boolean is an integer value, not necessarily of
/// type i1, the bits of which conform to getBooleanContents.
SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) {
DebugLoc dl = Bool.getNode()->getDebugLoc();
DebugLoc dl = Bool.getDebugLoc();
ISD::NodeType ExtendCode;
switch (TLI.getBooleanContents()) {
default:
@ -1033,7 +1033,7 @@ SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) {
void DAGTypeLegalizer::SplitInteger(SDValue Op,
MVT LoVT, MVT HiVT,
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
Op.getValueType().getSizeInBits() && "Invalid integer splitting!");
Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op);

2
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -2144,7 +2144,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
MVT InVT = InOp.getValueType();
assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match");
DebugLoc dl = InOp.getNode()->getDebugLoc();
DebugLoc dl = InOp.getDebugLoc();
// Check if InOp already has the right width.
if (InVT == NVT)

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2910,7 +2910,7 @@ static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
SelectionDAG &DAG) {
MVT VT = Base.getValueType();
return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(),
return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
VT, Base, DAG.getConstant(Offset, VT));
}

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -440,10 +440,10 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
MVT VT = Arg.getValueType();
unsigned VReg = MF.getRegInfo().
createVirtualRegister(TLI.getRegClassFor(VT));
Chain = DAG.getCopyToReg(Chain, Arg.getNode()->getDebugLoc(),
Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(),
VReg, Arg, InFlag);
InFlag = Chain.getValue(1);
Arg = DAG.getCopyFromReg(Chain, Arg.getNode()->getDebugLoc(),
Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(),
VReg, VT, InFlag);
Chain = Arg.getValue(1);
InFlag = Arg.getValue(2);

2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -761,7 +761,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
assert(Op.getValueSizeInBits() == BitWidth &&
"Mask size mismatches value type size!");
APInt NewMask = DemandedMask;
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Don't know anything.
KnownZero = KnownOne = APInt(BitWidth, 0);

2
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -470,7 +470,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,

4
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -114,7 +114,7 @@ namespace {
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
CallingConv::C, false, Callee, Args, DAG,
Op.getNode()->getDebugLoc());
Op.getDebugLoc());
return CallInfo.first;
}
@ -2488,7 +2488,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
CondCodeSDNode *CC = dyn_cast<CondCodeSDNode>(Op.getOperand(2));
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n");
SDValue lhs = Op.getOperand(0);

20
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1185,7 +1185,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// If we're comparing for equality to zero, expose the fact that this is
// implented as a ctlz/srl pair on ppc, so that the dag combiner can
@ -1242,7 +1242,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = (PtrVT == MVT::i64);
@ -1282,7 +1282,7 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
unsigned VarArgsNumGPR,
unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
if (Subtarget.isMachoABI()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
@ -1412,7 +1412,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
@ -2691,7 +2691,7 @@ SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) {
// When we pop the dynamic allocation we need to restore the SP link.
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Get the corect type for pointers.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@ -2895,7 +2895,7 @@ SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
}
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue();
@ -2941,7 +2941,7 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
}
SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
/*
The rounding mode is in bits 30:31 of FPSR, and has the following
settings:
@ -3061,7 +3061,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
}
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
@ -3740,7 +3740,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Create a stack slot that is 16-byte aligned.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
@ -4929,7 +4929,7 @@ bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
}
SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();

2
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -838,7 +838,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
SparcTargetLowering &TLI) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(TLI.getVarArgsFrameOffset(),

4
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -736,7 +736,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
bool is64Bit = Subtarget->is64Bit();
DebugLoc dl = N.getNode()->getDebugLoc();
DebugLoc dl = N.getDebugLoc();
DOUT << "MatchAddress: "; DEBUG(AM.dump());
// Limit recursion.
if (Depth > 5)
@ -1173,7 +1173,7 @@ SDNode *X86DAGToDAGISel::getTruncateTo8Bit(SDValue N0) {
assert(!Subtarget->is64Bit() &&
"getTruncateTo8Bit is only needed on x86-32!");
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
DebugLoc dl = N0.getNode()->getDebugLoc();
DebugLoc dl = N0.getDebugLoc();
// Ensure that the source register has an 8-bit subreg on 32-bit targets
unsigned Opc;

96
lib/Target/X86/X86ISelLowering.cpp
View File

@ -917,7 +917,7 @@ SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
/// LowerRET - Lower an ISD::RET node.
SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
SmallVector<CCValAssign, 16> RVLocs;
@ -1230,7 +1230,7 @@ SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
if (Flags.isByVal())
return FIN;
return DAG.getLoad(VA.getValVT(), Op.getNode()->getDebugLoc(), Root, FIN,
return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
PseudoSourceValue::getFixedStack(FI), 0);
}
@ -1238,7 +1238,7 @@ SDValue
X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
const Function* Fn = MF.getFunction();
if (Fn->hasExternalLinkage() &&
@ -2726,7 +2726,7 @@ static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
MVT EltVT = MaskVT.getVectorElementType();
unsigned NumElems = Mask.getNumOperands();
SmallVector<SDValue, 8> MaskVec;
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
@ -2968,7 +2968,7 @@ static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
}
if (Changed)
Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(),
Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
Mask.getValueType(),
&MaskVec[0], MaskVec.size());
return Mask;
@ -3045,7 +3045,7 @@ static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
SDValue Mask = Op.getOperand(2);
unsigned MaskNumElems = Mask.getNumOperands();
unsigned NumElems = MaskNumElems;
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Special handling of v4f32 -> v4i32.
if (VT != MVT::v4f32) {
// Find which element we want to splat.
@ -3095,7 +3095,7 @@ static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
MVT VT = Op.getValueType();
if (VT == PVT)
return Op;
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
unsigned NumElems = PVT.getVectorNumElements();
if (NumElems == 2) {
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
@ -3121,7 +3121,7 @@ static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
bool isZero, bool HasSSE2,
SelectionDAG &DAG) {
DebugLoc dl = V2.getNode()->getDebugLoc();
DebugLoc dl = V2.getDebugLoc();
MVT VT = V2.getValueType();
SDValue V1 = isZero
? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
@ -3211,7 +3211,7 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
if (NumNonZero > 8)
return SDValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue V(0, 0);
bool First = true;
for (unsigned i = 0; i < 16; ++i) {
@ -3257,7 +3257,7 @@ static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
if (NumNonZero > 4)
return SDValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue V(0, 0);
bool First = true;
for (unsigned i = 0; i < 8; ++i) {
@ -3295,7 +3295,7 @@ static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
SDValue
X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// All zero's are handled with pxor, all one's are handled with pcmpeqd.
if (ISD::isBuildVectorAllZeros(Op.getNode())
|| ISD::isBuildVectorAllOnes(Op.getNode())) {
@ -4059,7 +4059,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
SDValue V2 = Op.getOperand(1);
SDValue PermMask = Op.getOperand(2);
MVT VT = Op.getValueType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
unsigned NumElems = PermMask.getNumOperands();
bool isMMX = VT.getSizeInBits() == 64;
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
@ -4281,7 +4281,7 @@ SDValue
X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
SelectionDAG &DAG) {
MVT VT = Op.getValueType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
if (VT.getSizeInBits() == 8) {
SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
@ -4344,7 +4344,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
}
MVT VT = Op.getValueType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// TODO: handle v16i8.
if (VT.getSizeInBits() == 16) {
SDValue Vec = Op.getOperand(0);
@ -4417,7 +4417,7 @@ SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
MVT VT = Op.getValueType();
MVT EVT = VT.getVectorElementType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
@ -4464,7 +4464,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
if (EVT == MVT::i8)
return SDValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
@ -4483,7 +4483,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
SDValue
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
if (Op.getValueType() == MVT::v2f32)
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
@ -4578,7 +4578,7 @@ SDValue
X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
return LowerGlobalAddress(GV, Op.getNode()->getDebugLoc(), Offset, DAG);
return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
@ -4743,7 +4743,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
MVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
@ -4796,7 +4796,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Subtarget->is64Bit())
return SDValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
unsigned Size = SrcVT.getSizeInBits()/8;
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
@ -4880,7 +4880,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
}
*/
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Build some magic constants.
std::vector<Constant*> CV0;
@ -4941,7 +4941,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// FP constant to bias correct the final result.
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
MVT::f64);
@ -4987,7 +4987,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
SDValue N0 = Op.getOperand(0);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
// optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
@ -5012,7 +5012,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
std::pair<SDValue,SDValue> X86TargetLowering::
FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
Op.getValueType().getSimpleVT() >= MVT::i16 &&
"Unknown FP_TO_SINT to lower!");
@ -5069,12 +5069,12 @@ SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
if (FIST.getNode() == 0) return SDValue();
// Load the result.
return DAG.getLoad(Op.getValueType(), Op.getNode()->getDebugLoc(),
return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
FIST, StackSlot, NULL, 0);
}
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT EltVT = VT;
if (VT.isVector())
@ -5100,7 +5100,7 @@ SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
}
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT EltVT = VT;
unsigned EltNum = 1;
@ -5139,7 +5139,7 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT SrcVT = Op1.getValueType();
@ -5212,7 +5212,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
// Lower (X & (1 << N)) == 0 to BT(X, N).
@ -5283,7 +5283,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
if (isFP) {
unsigned SSECC = 8;
@ -5396,7 +5396,7 @@ static bool isX86LogicalCmp(unsigned Opc) {
SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
bool addTest = true;
SDValue Cond = Op.getOperand(0);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue CC;
if (Cond.getOpcode() == ISD::SETCC)
@ -5471,7 +5471,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0);
SDValue Cond = Op.getOperand(1);
SDValue Dest = Op.getOperand(2);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue CC;
if (Cond.getOpcode() == ISD::SETCC)
@ -5594,7 +5594,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) {
assert(Subtarget->isTargetCygMing() &&
"This should be used only on Cygwin/Mingw targets");
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Get the inputs.
SDValue Chain = Op.getOperand(0);
@ -5852,7 +5852,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
if (!Subtarget->is64Bit()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
@ -5919,7 +5919,7 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
SDValue SrcPtr = Op.getOperand(2);
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
DAG.getIntPtrConstant(24), 8, false,
@ -5928,7 +5928,7 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
SDValue
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
@ -6125,7 +6125,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
if (Depth > 0) {
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
@ -6148,7 +6148,7 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true);
MVT VT = Op.getValueType();
DebugLoc dl = Op.getNode()->getDebugLoc(); // FIXME probably not meaningful
DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
@ -6168,7 +6168,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
SDValue Chain = Op.getOperand(0);
SDValue Offset = Op.getOperand(1);
SDValue Handler = Op.getOperand(2);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
getPointerTy());
@ -6192,7 +6192,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
@ -6352,7 +6352,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
const TargetFrameInfo &TFI = *TM.getFrameInfo();
unsigned StackAlignment = TFI.getStackAlignment();
MVT VT = Op.getValueType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// Save FP Control Word to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
@ -6392,7 +6392,7 @@ SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
if (VT == MVT::i8) {
@ -6425,7 +6425,7 @@ SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
if (VT == MVT::i8) {
@ -6453,7 +6453,7 @@ SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
// ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
@ -6505,7 +6505,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
SDValue RHS = N->getOperand(1);
unsigned BaseOp = 0;
unsigned Cond = 0;
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: assert(0 && "Unknown ovf instruction!");
@ -6549,7 +6549,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
MVT T = Op.getValueType();
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
unsigned Reg = 0;
unsigned size = 0;
switch(T.getSimpleVT()) {
@ -6582,7 +6582,7 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
assert(Subtarget->is64Bit() && "Result not type legalized?");
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = Op.getOperand(0);
DebugLoc dl = Op.getNode()->getDebugLoc();
DebugLoc dl = Op.getDebugLoc();
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
@ -8243,7 +8243,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
if (GA) {
if (hasMemory)
Op = LowerGlobalAddress(GA->getGlobal(), Op.getNode()->getDebugLoc(),
Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
Offset, DAG);
else
Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),