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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224080 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1741,7 +1741,7 @@ EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
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return VT.changeVectorElementTypeToInteger();
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return VT.changeVectorElementTypeToInteger();
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}
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}
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/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
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/// Helper for getByValTypeAlignment to determine
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/// the desired ByVal argument alignment.
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/// the desired ByVal argument alignment.
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static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
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static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
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if (MaxAlign == 16)
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if (MaxAlign == 16)
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@ -1766,7 +1766,7 @@ static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
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}
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}
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}
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}
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/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
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/// Return the desired alignment for ByVal aggregate
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/// function arguments in the caller parameter area. For X86, aggregates
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/// function arguments in the caller parameter area. For X86, aggregates
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/// that contain SSE vectors are placed at 16-byte boundaries while the rest
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/// that contain SSE vectors are placed at 16-byte boundaries while the rest
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/// are at 4-byte boundaries.
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/// are at 4-byte boundaries.
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@ -1785,7 +1785,7 @@ unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
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return Align;
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return Align;
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}
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}
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/// getOptimalMemOpType - Returns the target specific optimal type for load
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/// Returns the target specific optimal type for load
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/// and store operations as a result of memset, memcpy, and memmove
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/// and store operations as a result of memset, memcpy, and memmove
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/// lowering. If DstAlign is zero that means it's safe to destination
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/// lowering. If DstAlign is zero that means it's safe to destination
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/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
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/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
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@ -1851,7 +1851,7 @@ X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
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return true;
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return true;
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}
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}
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/// getJumpTableEncoding - Return the entry encoding for a jump table in the
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/// Return the entry encoding for a jump table in the
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/// current function. The returned value is a member of the
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/// current function. The returned value is a member of the
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/// MachineJumpTableInfo::JTEntryKind enum.
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/// MachineJumpTableInfo::JTEntryKind enum.
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unsigned X86TargetLowering::getJumpTableEncoding() const {
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unsigned X86TargetLowering::getJumpTableEncoding() const {
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@ -1877,8 +1877,7 @@ X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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MCSymbolRefExpr::VK_GOTOFF, Ctx);
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MCSymbolRefExpr::VK_GOTOFF, Ctx);
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}
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}
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/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
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/// Returns relocation base for the given PIC jumptable.
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/// jumptable.
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SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
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SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const {
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SelectionDAG &DAG) const {
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if (!Subtarget->is64Bit())
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if (!Subtarget->is64Bit())
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@ -1888,9 +1887,8 @@ SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
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return Table;
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return Table;
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}
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}
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/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
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/// This returns the relocation base for the given PIC jumptable,
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/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
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/// the same as getPICJumpTableRelocBase, but as an MCExpr.
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/// MCExpr.
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const MCExpr *X86TargetLowering::
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const MCExpr *X86TargetLowering::
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getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
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getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
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MCContext &Ctx) const {
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MCContext &Ctx) const {
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@ -2149,7 +2147,7 @@ X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
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return VT.bitsLT(MinVT) ? MinVT : VT;
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return VT.bitsLT(MinVT) ? MinVT : VT;
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}
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}
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/// LowerCallResult - Lower the result values of a call into the
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/// Lower the result values of a call into the
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/// appropriate copies out of appropriate physical registers.
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/// appropriate copies out of appropriate physical registers.
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///
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///
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SDValue
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SDValue
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@ -2229,8 +2227,7 @@ callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
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return StackStructReturn;
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return StackStructReturn;
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}
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}
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/// ArgsAreStructReturn - Determines whether a function uses struct
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/// Determines whether a function uses struct return semantics.
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/// return semantics.
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static StructReturnType
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static StructReturnType
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argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
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argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
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if (Ins.empty())
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if (Ins.empty())
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@ -2244,10 +2241,9 @@ argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
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return StackStructReturn;
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return StackStructReturn;
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}
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}
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/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
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/// Make a copy of an aggregate at address specified by "Src" to address
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/// by "Src" to address "Dst" with size and alignment information specified by
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/// "Dst" with size and alignment information specified by the specific
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/// the specific parameter attribute. The copy will be passed as a byval
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/// parameter attribute. The copy will be passed as a byval function parameter.
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/// function parameter.
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static SDValue
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static SDValue
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CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
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CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
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ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
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ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
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@ -2259,7 +2255,7 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
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MachinePointerInfo(), MachinePointerInfo());
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MachinePointerInfo(), MachinePointerInfo());
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}
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}
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/// IsTailCallConvention - Return true if the calling convention is one that
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/// Return true if the calling convention is one that
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/// supports tail call optimization.
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/// supports tail call optimization.
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static bool IsTailCallConvention(CallingConv::ID CC) {
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static bool IsTailCallConvention(CallingConv::ID CC) {
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return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
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return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
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@ -2284,7 +2280,7 @@ bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
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return true;
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return true;
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}
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}
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/// FuncIsMadeTailCallSafe - Return true if the function is being made into
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/// Return true if the function is being made into
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/// a tailcall target by changing its ABI.
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/// a tailcall target by changing its ABI.
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static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
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static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
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bool GuaranteedTailCallOpt) {
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bool GuaranteedTailCallOpt) {
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@ -2696,7 +2692,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
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false, false, 0);
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false, false, 0);
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}
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}
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/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
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/// Emit a load of return address if tail call
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/// optimization is performed and it is required.
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/// optimization is performed and it is required.
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SDValue
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SDValue
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X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
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X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
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@ -2713,7 +2709,7 @@ X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
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return SDValue(OutRetAddr.getNode(), 1);
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return SDValue(OutRetAddr.getNode(), 1);
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}
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}
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/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
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/// Emit a store of the return address if tail call
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/// optimization is performed and it is required (FPDiff!=0).
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/// optimization is performed and it is required (FPDiff!=0).
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static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
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static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
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SDValue Chain, SDValue RetAddrFrIdx,
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SDValue Chain, SDValue RetAddrFrIdx,
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@ -24571,7 +24567,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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}
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}
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/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
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/// Return 'true' if this vector operation is "horizontal"
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/// and return the operands for the horizontal operation in LHS and RHS. A
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/// and return the operands for the horizontal operation in LHS and RHS. A
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/// horizontal operation performs the binary operation on successive elements
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/// horizontal operation performs the binary operation on successive elements
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/// of its first operand, then on successive elements of its second operand,
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/// of its first operand, then on successive elements of its second operand,
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@ -24697,7 +24693,7 @@ static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
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return true;
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return true;
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}
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}
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/// PerformFADDCombine - Do target-specific dag combines on floating point adds.
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/// Do target-specific dag combines on floating point adds.
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static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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@ -24712,7 +24708,7 @@ static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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}
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}
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/// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
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/// Do target-specific dag combines on floating point subs.
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static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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@ -24727,8 +24723,7 @@ static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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}
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}
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/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
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/// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
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/// X86ISD::FXOR nodes.
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static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
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assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
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assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
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// F[X]OR(0.0, x) -> x
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// F[X]OR(0.0, x) -> x
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@ -24742,8 +24737,7 @@ static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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return SDValue();
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}
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}
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/// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
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/// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
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/// X86ISD::FMAX nodes.
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static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
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assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
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@ -24764,7 +24758,7 @@ static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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N->getOperand(0), N->getOperand(1));
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N->getOperand(0), N->getOperand(1));
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}
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}
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/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
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/// Do target-specific dag combines on X86ISD::FAND nodes.
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static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
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// FAND(0.0, x) -> 0.0
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// FAND(0.0, x) -> 0.0
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// FAND(x, 0.0) -> 0.0
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// FAND(x, 0.0) -> 0.0
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@ -24777,7 +24771,7 @@ static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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return SDValue();
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}
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}
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/// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
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/// Do target-specific dag combines on X86ISD::FANDN nodes
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static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
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// FANDN(x, 0.0) -> 0.0
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// FANDN(x, 0.0) -> 0.0
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// FANDN(0.0, x) -> x
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// FANDN(0.0, x) -> x
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