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[X86] Generate VPSHUFB for in-place v16i16 shuffles

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This used to resort to splitting the 256-bit operation into two 128-bit
shuffles and then recombining the results.

Fixes <rdar://problem/16167303>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-03-25 17:47:06 +00:00
parent 9526911809
commit 6f4f46cf11
2 changed files with 47 additions and 0 deletions
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25
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6576,6 +6576,25 @@ LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
return NewV;
}
/// \brief v16i16 shuffles
///
/// FIXME: We only support generation of a single pshufb currently. We can
/// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
/// well (e.g 2 x pshufb + 1 x por).
static SDValue
LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1);
SDLoc dl(SVOp);
if (V2.getOpcode() != ISD::UNDEF)
return SDValue();
SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
return getPSHUFB(MaskVals, V1, dl, DAG);
}
// v16i8 shuffles - Prefer shuffles in the following order:
// 1. [ssse3] 1 x pshufb
// 2. [ssse3] 2 x pshufb + 1 x por
@ -7635,6 +7654,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
return NewOp;
}
if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
if (NewOp.getNode())
return NewOp;
}
if (VT == MVT::v16i8) {
SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
if (NewOp.getNode())

22
test/CodeGen/X86/vec_shuffle-40.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s
define void @shuffle_v16i16(<16 x i16>* %a) {
; CHECK-LABEL: shuffle_v16i16:
; CHECK: vpshufb {{.*}}%ymm
; CHECK-NOT: vpshufb {{.*}}%xmm
entry:
%0 = load <16 x i16>* %a, align 32
%shuffle = shufflevector <16 x i16> %0, <16 x i16> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
store <16 x i16> %shuffle, <16 x i16>* %a, align 32
ret void
}
define void @shuffle_v16i16_lanecrossing(<16 x i16>* %a) {
; CHECK-LABEL: shuffle_v16i16_lanecrossing:
; CHECK-NOT: vpshufb {{.*}}%ymm
entry:
%0 = load <16 x i16>* %a, align 32
%shuffle = shufflevector <16 x i16> %0, <16 x i16> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 13, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
store <16 x i16> %shuffle, <16 x i16>* %a, align 32
ret void
}