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Fix a bug that prevented x86-64 from using rep.movsq for

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8-byte-aligned data.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-04-12 02:35:39 +00:00
parent 6795ebb663
commit 6f836adafe
2 changed files with 3 additions and 3 deletions
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4
lib/Target/X86/X86ISelLowering.cpp
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@ -4621,7 +4621,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
ValReg = X86::EAX;
Val = (Val << 8) | Val;
Val = (Val << 16) | Val;
if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
AVT = MVT::i64;
ValReg = X86::RAX;
Val = (Val << 32) | Val;
@ -4740,7 +4740,7 @@ SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
break;
case 0: // DWORD aligned
AVT = MVT::i32;
if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
AVT = MVT::i64;
break;
default: // Byte aligned

2
test/CodeGen/X86/byval2.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
%struct.s = type { i64, i64, i64 }