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Fully general expansion of integer shift of any size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68134 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1231,6 +1231,78 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
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return false;
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}
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/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
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/// of any size.
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bool DAGTypeLegalizer::
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ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
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SDValue Amt = N->getOperand(1);
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MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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MVT ShTy = Amt.getValueType();
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unsigned NVTBits = NVT.getSizeInBits();
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assert(isPowerOf2_32(NVTBits) &&
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"Expanded integer type size not a power of two!");
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DebugLoc dl = N->getDebugLoc();
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// Get the incoming operand to be shifted.
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SDValue InL, InH;
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GetExpandedInteger(N->getOperand(0), InL, InH);
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SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
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SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
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SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
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Amt, NVBitsNode, ISD::SETULT);
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SDValue Lo1, Hi1, Lo2, Hi2;
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switch (N->getOpcode()) {
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default: assert(0 && "Unknown shift");
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case ISD::SHL:
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// ShAmt < NVTBits
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Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
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Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
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// ShAmt >= NVTBits
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Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
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Hi2 = DAG.getNode(ISD::OR, dl, NVT,
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DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
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DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
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Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
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Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
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return true;
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case ISD::SRL:
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// ShAmt < NVTBits
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Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
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Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
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// ShAmt >= NVTBits
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Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
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Lo2 = DAG.getNode(ISD::OR, dl, NVT,
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DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
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DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
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Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
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Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
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return true;
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case ISD::SRA:
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// ShAmt < NVTBits
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Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
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DAG.getConstant(NVTBits-1, ShTy));
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Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
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// ShAmt >= NVTBits
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Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
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Lo2 = DAG.getNode(ISD::OR, dl, NVT,
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DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
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DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
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Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
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Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
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return true;
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}
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return false;
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}
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void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
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SDValue &Lo, SDValue &Hi) {
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DebugLoc dl = N->getDebugLoc();
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@ -1792,10 +1864,15 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
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else if (VT == MVT::i128)
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LC = RTLIB::SRA_I128;
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}
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
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if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
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SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
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SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
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return;
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}
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if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
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assert(0 && "Unsupported shift!");
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}
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void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
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@ -353,6 +353,7 @@ private:
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void ExpandShiftByConstant(SDNode *N, unsigned Amt,
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SDValue &Lo, SDValue &Hi);
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bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
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bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
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// Integer Operand Expansion.
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bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
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9
test/CodeGen/X86/shift-i128.ll
Normal file
9
test/CodeGen/X86/shift-i128.ll
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@ -0,0 +1,9 @@
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; RUN: llvm-as < %s | llc -march=x86
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; RUN: llvm-as < %s | llc -march=x86-64
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define void @t(i128 %x, i128 %a, i128* nocapture %r) nounwind {
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entry:
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%0 = lshr i128 %x, %a
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store i128 %0, i128* %r, align 16
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ret void
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}
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9
test/CodeGen/X86/shift-i256.ll
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9
test/CodeGen/X86/shift-i256.ll
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@ -0,0 +1,9 @@
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; RUN: llvm-as < %s | llc -march=x86
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; RUN: llvm-as < %s | llc -march=x86-64
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define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
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entry:
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%0 = ashr i256 %x, %a
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store i256 %0, i256* %r
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ret void
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}
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