From 6fd78ec8a216f659ce7c0c9912bb81e29595fed9 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 10 Dec 2009 20:59:45 +0000
Subject: [PATCH] It's not safe to coalesce a move where src and dst registers
 have different subregister indices. e.g.: %reg16404:1<def> = MOV8rr
 %reg16412:2<kill>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91061 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SimpleRegisterCoalescing.cpp    |  8 ++++-
 test/CodeGen/X86/2009-12-12-CoalescerBug.ll | 40 +++++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/X86/2009-12-12-CoalescerBug.ll

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 94f17cec9b4..5ebe557d1a3 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1317,7 +1317,13 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
                       "coalesced to another register.\n");
       return false;  // Not coalescable.
     }
-  } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
+  } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
+    if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
+      // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
+      Again = true;
+      return false;  // Not coalescable.
+    }
+  } else {
     llvm_unreachable("Unrecognized copy instruction!");
   }
 
diff --git a/test/CodeGen/X86/2009-12-12-CoalescerBug.ll b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll
new file mode 100644
index 00000000000..4e8f5fdc530
--- /dev/null
+++ b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+
+define i32 @do_loop(i32* nocapture %sdp, i32* nocapture %ddp, i8* %mdp, i8* nocapture %cdp, i32 %w) nounwind readonly optsize ssp {
+entry:
+  br label %bb
+
+bb:                                               ; preds = %bb5, %entry
+  %mask.1.in = load i8* undef, align 1            ; <i8> [#uses=3]
+  %0 = icmp eq i8 %mask.1.in, 0                   ; <i1> [#uses=1]
+  br i1 %0, label %bb5, label %bb1
+
+bb1:                                              ; preds = %bb
+  br i1 undef, label %bb2, label %bb3
+
+bb2:                                              ; preds = %bb1
+; CHECK: %bb2
+; CHECK: movb %ch, %al
+  %1 = zext i8 %mask.1.in to i32                  ; <i32> [#uses=1]
+  %2 = zext i8 undef to i32                       ; <i32> [#uses=1]
+  %3 = mul i32 %2, %1                             ; <i32> [#uses=1]
+  %4 = add i32 %3, 1                              ; <i32> [#uses=1]
+  %5 = add i32 %4, 0                              ; <i32> [#uses=1]
+  %6 = lshr i32 %5, 8                             ; <i32> [#uses=1]
+  %retval12.i = trunc i32 %6 to i8                ; <i8> [#uses=1]
+  br label %bb3
+
+bb3:                                              ; preds = %bb2, %bb1
+  %mask.0.in = phi i8 [ %retval12.i, %bb2 ], [ %mask.1.in, %bb1 ] ; <i8> [#uses=1]
+  %7 = icmp eq i8 %mask.0.in, 0                   ; <i1> [#uses=1]
+  br i1 %7, label %bb5, label %bb4
+
+bb4:                                              ; preds = %bb3
+  br label %bb5
+
+bb5:                                              ; preds = %bb4, %bb3, %bb
+  br i1 undef, label %bb6, label %bb
+
+bb6:                                              ; preds = %bb5
+  ret i32 undef
+}