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__builtin_ia32_loadup{s|d}, __builtin_ia32_storeup{s|d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27561 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -133,7 +133,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// SIMD store ops
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// SIMD store ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
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def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
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Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
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Intrinsic<[llvm_void_ty, llvm_ptr_ty,
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llvm_v4f32_ty], [IntrWriteMem]>;
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}
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}
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// Cacheability support ops
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// Cacheability support ops
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@ -267,6 +268,19 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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llvm_int_ty], [InstrNoMem]>;
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llvm_int_ty], [InstrNoMem]>;
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}
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}
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// SIMD load ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">,
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Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>;
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}
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// SIMD store ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
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Intrinsic<[llvm_void_ty, llvm_ptr_ty,
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llvm_v2f64_ty], [IntrWriteMem]>;
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}
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// Misc.
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// Misc.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
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def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
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