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Add a -regalloc=default option that chooses a register allocator based on the -O

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optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-05-27 23:57:25 +00:00
parent 1fa1c7b23b
commit 700bfada63
7 changed files with 28 additions and 13 deletions
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2
test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+neon -O0
; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan
; This test would crash the rewriter when trying to handle a spill after one of
; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register.

2
test/CodeGen/X86/2008-05-21-CoalescerBug.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5
; RUN: llc < %s -march=x86 -O0 -fast-isel=false -regalloc=linearscan | grep mov | count 5
; PR2343
%llvm.dbg.anchor.type = type { i32, i32 }

2
test/CodeGen/X86/fast-isel-bc.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
; RUN: llc < %s -O0 -regalloc=linearscan -march=x86-64 -mattr=+mmx | FileCheck %s
; PR4684
target datalayout =

2
test/CodeGen/X86/inline-asm-tied.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2
; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl %edx, 12(%esp)} | count 2
; rdar://6992609
target triple = "i386-apple-darwin9.0"