mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[SKX] Enabling load/store instructions: encoding
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS, Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
c568629589
commit
7017934668
@ -1433,104 +1433,176 @@ def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
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// AVX-512 - Aligned and unaligned load and store
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//
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multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
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X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d,
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ValueType vt, bit IsReMaterializable = 1> {
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multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
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RegisterClass KRC, RegisterClass RC,
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ValueType vt, ValueType zvt, X86MemOperand memop,
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Domain d, bit IsReMaterializable = 1> {
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let hasSideEffects = 0 in {
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def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
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EVEX;
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
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d>, EVEX;
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def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
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!strconcat(asm,
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" \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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[], d>, EVEX, EVEX_KZ;
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
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"${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
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}
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
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def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(asm, " \t{$src, $dst|$dst, $src}"),
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[(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
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let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
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def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2),
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!strconcat(asm,
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" \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
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EVEX, EVEX_K;
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let mayLoad = 1 in
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def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, x86memop:$src2),
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!strconcat(asm,
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" \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
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[], d>, EVEX, EVEX_K;
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
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SchedRW = [WriteLoad] in
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def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
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d>, EVEX;
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let AddedComplexity = 20 in {
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let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
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let hasSideEffects = 0 in
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def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, RC:$src1),
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!strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src1}"),
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[(set RC:$dst, (vt (vselect KRC:$mask,
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(vt RC:$src1),
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(vt RC:$src0))))],
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d>, EVEX, EVEX_K;
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let mayLoad = 1, SchedRW = [WriteLoad] in
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def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, memop:$src1),
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!strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src1}"),
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[(set RC:$dst, (vt
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(vselect KRC:$mask,
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(vt (bitconvert (ld_frag addr:$src1))),
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(vt RC:$src0))))],
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d>, EVEX, EVEX_K;
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}
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let mayLoad = 1, SchedRW = [WriteLoad] in
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def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, memop:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
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"${dst} {${mask}} {z}, $src}"),
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[(set RC:$dst, (vt
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(vselect KRC:$mask,
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(vt (bitconvert (ld_frag addr:$src))),
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(vt (bitconvert (zvt immAllZerosV))))))],
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d>, EVEX, EVEX_KZ;
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}
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let mayLoad = 1 in
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def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, x86memop:$src2),
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!strconcat(asm,
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" \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
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[], d>, EVEX, EVEX_KZ;
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}
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multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
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X86MemOperand x86memop, PatFrag store_frag,
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string asm, Domain d, ValueType vt> {
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multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
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string elty, string elsz, string vsz512,
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string vsz256, string vsz128, Domain d,
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Predicate prd, bit IsReMaterializable = 1> {
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let Predicates = [prd] in
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defm Z : avx512_load<opc, OpcodeStr,
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!cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
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!cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
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!cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
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!cast<X86MemOperand>(elty##"512mem"), d,
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IsReMaterializable>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_load<opc, OpcodeStr,
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!cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
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"v"##vsz256##elty##elsz, "v4i64")),
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!cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
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!cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
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!cast<X86MemOperand>(elty##"256mem"), d,
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IsReMaterializable>, EVEX_V256;
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defm Z128 : avx512_load<opc, OpcodeStr,
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!cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
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"v"##vsz128##elty##elsz, "v2i64")),
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!cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
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!cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
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!cast<X86MemOperand>(elty##"128mem"), d,
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IsReMaterializable>, EVEX_V128;
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}
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}
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multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
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ValueType OpVT, RegisterClass KRC, RegisterClass RC,
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X86MemOperand memop, Domain d> {
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
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EVEX;
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let Constraints = "$src1 = $dst" in
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def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2),
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!strconcat(asm,
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" \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
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def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
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EVEX, EVEX_K;
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def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
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def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src),
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!strconcat(asm,
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" \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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[], d>, EVEX, EVEX_KZ;
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}
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let mayStore = 1 in {
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def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
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!strconcat(asm, " \t{$src, $dst|$dst, $src}"),
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[(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
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def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
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def mrk : AVX512PI<opc, MRMDestMem, (outs),
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(ins x86memop:$dst, KRC:$mask, RC:$src),
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!strconcat(asm,
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" \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
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(ins memop:$dst, KRC:$mask, RC:$src),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
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[], d>, EVEX, EVEX_K;
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def mrkz : AVX512PI<opc, MRMDestMem, (outs),
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(ins x86memop:$dst, KRC:$mask, RC:$src),
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!strconcat(asm,
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" \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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[], d>, EVEX, EVEX_KZ;
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}
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}
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defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
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"vmovaps", SSEPackedSingle, v16f32>,
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avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
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"vmovaps", SSEPackedSingle, v16f32>,
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PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
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"vmovapd", SSEPackedDouble, v8f64>,
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avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
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"vmovapd", SSEPackedDouble, v8f64>,
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PD, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
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"vmovups", SSEPackedSingle, v16f32>,
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avx512_store<0x11, VR512, VK16WM, f512mem, store,
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"vmovups", SSEPackedSingle, v16f32>,
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PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
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"vmovupd", SSEPackedDouble, v8f64, 0>,
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avx512_store<0x11, VR512, VK8WM, f512mem, store,
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"vmovupd", SSEPackedDouble, v8f64>,
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PD, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
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string st_suff_512, string st_suff_256,
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string st_suff_128, string elty, string elsz,
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string vsz512, string vsz256, string vsz128,
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Domain d, Predicate prd> {
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let Predicates = [prd] in
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defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
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!cast<ValueType>("v"##vsz512##elty##elsz),
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!cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
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!cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
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!cast<ValueType>("v"##vsz256##elty##elsz),
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!cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
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!cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
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defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
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!cast<ValueType>("v"##vsz128##elty##elsz),
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!cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
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!cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
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}
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}
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defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
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"16", "8", "4", SSEPackedSingle, HasAVX512>,
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avx512_store_vl<0x29, "vmovaps", "alignedstore",
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"512", "256", "", "f", "32", "16", "8", "4",
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SSEPackedSingle, HasAVX512>,
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PS, EVEX_CD8<32, CD8VF>;
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defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
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"8", "4", "2", SSEPackedDouble, HasAVX512>,
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avx512_store_vl<0x29, "vmovapd", "alignedstore",
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"512", "256", "", "f", "64", "8", "4", "2",
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SSEPackedDouble, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
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"16", "8", "4", SSEPackedSingle, HasAVX512>,
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avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
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"16", "8", "4", SSEPackedSingle, HasAVX512>,
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PS, EVEX_CD8<32, CD8VF>;
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defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
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"8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
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avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
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"8", "4", "2", SSEPackedDouble, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
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(bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
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(bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
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(VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
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def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
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@ -1546,75 +1618,80 @@ def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
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(VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
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VR512:$src)>;
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defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
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"vmovdqa32", SSEPackedInt, v16i32>,
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avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
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"vmovdqa32", SSEPackedInt, v16i32>,
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PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
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"vmovdqa64", SSEPackedInt, v8i64>,
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avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
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"vmovdqa64", SSEPackedInt, v8i64>,
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PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
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defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
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"vmovdqu32", SSEPackedInt, v16i32>,
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avx512_store<0x7F, VR512, VK16WM, i512mem, store,
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"vmovdqu32", SSEPackedInt, v16i32>,
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XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
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"vmovdqu64", SSEPackedInt, v8i64>,
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avx512_store<0x7F, VR512, VK8WM, i512mem, store,
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"vmovdqu64", SSEPackedInt, v8i64>,
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XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
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defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
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"16", "8", "4", SSEPackedInt, HasAVX512>,
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avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
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"512", "256", "", "i", "32", "16", "8", "4",
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SSEPackedInt, HasAVX512>,
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PD, EVEX_CD8<32, CD8VF>;
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defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
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"8", "4", "2", SSEPackedInt, HasAVX512>,
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avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
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"512", "256", "", "i", "64", "8", "4", "2",
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SSEPackedInt, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
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"64", "32", "16", SSEPackedInt, HasBWI>,
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avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
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"i", "8", "64", "32", "16", SSEPackedInt,
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HasBWI>, XD, EVEX_CD8<8, CD8VF>;
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defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
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"32", "16", "8", SSEPackedInt, HasBWI>,
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avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
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||||
"i", "16", "32", "16", "8", SSEPackedInt,
|
||||
HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
|
||||
|
||||
defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
|
||||
"16", "8", "4", SSEPackedInt, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
|
||||
"i", "32", "16", "8", "4", SSEPackedInt,
|
||||
HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
|
||||
"8", "4", "2", SSEPackedInt, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
|
||||
"i", "64", "8", "4", "2", SSEPackedInt,
|
||||
HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
|
||||
(v16i32 immAllZerosV), GR16:$mask)),
|
||||
(VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
|
||||
(VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
|
||||
|
||||
def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
|
||||
(bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
|
||||
(VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
|
||||
(bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
|
||||
(VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
|
||||
|
||||
def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
|
||||
GR16:$mask),
|
||||
(VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
|
||||
GR16:$mask),
|
||||
(VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
|
||||
VR512:$src)>;
|
||||
def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
|
||||
GR8:$mask),
|
||||
(VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
|
||||
GR8:$mask),
|
||||
(VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
|
||||
VR512:$src)>;
|
||||
|
||||
let AddedComplexity = 20 in {
|
||||
def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
|
||||
(bc_v8i64 (v16i32 immAllZerosV)))),
|
||||
(VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
|
||||
(bc_v8i64 (v16i32 immAllZerosV)))),
|
||||
(VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
|
||||
|
||||
def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
|
||||
(v8i64 VR512:$src))),
|
||||
(VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
|
||||
(v8i64 VR512:$src))),
|
||||
(VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
|
||||
VK8), VR512:$src)>;
|
||||
|
||||
def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
|
||||
(v16i32 immAllZerosV))),
|
||||
(VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
|
||||
(VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
|
||||
|
||||
def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
|
||||
(v16i32 VR512:$src))),
|
||||
(VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
|
||||
|
||||
def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
|
||||
(v16f32 VR512:$src2))),
|
||||
(VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
|
||||
def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
|
||||
(v8f64 VR512:$src2))),
|
||||
(VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
|
||||
def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2))),
|
||||
(VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
|
||||
def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2))),
|
||||
(VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
|
||||
(v16i32 VR512:$src))),
|
||||
(VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
|
||||
}
|
||||
|
||||
// Move Int Doubleword to Packed Double Int
|
||||
//
|
||||
def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
|
||||
|
||||
@ -311,6 +311,8 @@ def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
|
||||
// 512-bit load pattern fragments
|
||||
def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
|
||||
def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
|
||||
def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
|
||||
def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
|
||||
def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
|
||||
def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
|
||||
|
||||
|
||||
@ -601,10 +601,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
|
||||
// AVX-512 foldable instructions
|
||||
{ X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
|
||||
{ X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
|
||||
{ X86::VMOVDQA32rr, X86::VMOVDQA32rm, TB_ALIGN_64 },
|
||||
{ X86::VMOVDQA64rr, X86::VMOVDQA64rm, TB_ALIGN_64 },
|
||||
{ X86::VMOVDQU32rr, X86::VMOVDQU32rm, 0 },
|
||||
{ X86::VMOVDQU64rr, X86::VMOVDQU64rm, 0 },
|
||||
{ X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
|
||||
{ X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
|
||||
{ X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
|
||||
{ X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
|
||||
{ X86::VPABSDZrr, X86::VPABSDZrm, 0 },
|
||||
{ X86::VPABSQZrr, X86::VPABSQZrm, 0 },
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
; CHECK-LABEL: test1
|
||||
; CHECK: vcmpleps
|
||||
; CHECK: vmovups
|
||||
; CHECK: vmovaps
|
||||
; CHECK: ret
|
||||
define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
|
||||
%mask = fcmp ole <16 x float> %x, %y
|
||||
@ -12,7 +12,7 @@ define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
|
||||
|
||||
; CHECK-LABEL: test2
|
||||
; CHECK: vcmplepd
|
||||
; CHECK: vmovupd
|
||||
; CHECK: vmovapd
|
||||
; CHECK: ret
|
||||
define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
|
||||
%mask = fcmp ole <8 x double> %x, %y
|
||||
@ -22,7 +22,7 @@ define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
|
||||
|
||||
; CHECK-LABEL: test3
|
||||
; CHECK: vpcmpeqd (%rdi)
|
||||
; CHECK: vmovdqu32
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %yp) nounwind {
|
||||
%y = load <16 x i32>* %yp, align 4
|
||||
@ -33,7 +33,7 @@ define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %yp) nounwin
|
||||
|
||||
; CHECK-LABEL: @test4_unsigned
|
||||
; CHECK: vpcmpnltud
|
||||
; CHECK: vmovdqu32
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y) nounwind {
|
||||
%mask = icmp uge <16 x i32> %x, %y
|
||||
@ -43,7 +43,7 @@ define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y) nounwind {
|
||||
|
||||
; CHECK-LABEL: test5
|
||||
; CHECK: vpcmpeqq {{.*}}%k1
|
||||
; CHECK: vmovdqu64 {{.*}}%k1
|
||||
; CHECK: vmovdqa64 {{.*}}%k1
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
|
||||
%mask = icmp eq <8 x i64> %x, %y
|
||||
@ -53,7 +53,7 @@ define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
|
||||
|
||||
; CHECK-LABEL: test6_unsigned
|
||||
; CHECK: vpcmpnleuq {{.*}}%k1
|
||||
; CHECK: vmovdqu64 {{.*}}%k1
|
||||
; CHECK: vmovdqa64 {{.*}}%k1
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test6_unsigned(<8 x i64> %x, <8 x i64> %y) nounwind {
|
||||
%mask = icmp ugt <8 x i64> %x, %y
|
||||
|
||||
@ -449,6 +449,294 @@
|
||||
// CHECK: encoding: [0x62,0xf1,0x64,0x58,0x5d,0x9a,0xfc,0xfd,0xff,0xff]
|
||||
vminps -516(%rdx){1to16}, %zmm3, %zmm3
|
||||
|
||||
// CHECK: vmovapd %zmm14, %zmm7
|
||||
// CHECK: encoding: [0x62,0xd1,0xfd,0x48,0x28,0xfe]
|
||||
vmovapd %zmm14, %zmm7
|
||||
|
||||
// CHECK: vmovapd %zmm14, %zmm7 {%k5}
|
||||
// CHECK: encoding: [0x62,0xd1,0xfd,0x4d,0x28,0xfe]
|
||||
vmovapd %zmm14, %zmm7 {%k5}
|
||||
|
||||
// CHECK: vmovapd %zmm14, %zmm7 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0xd1,0xfd,0xcd,0x28,0xfe]
|
||||
vmovapd %zmm14, %zmm7 {%k5} {z}
|
||||
|
||||
// CHECK: vmovapd (%rcx), %zmm7
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x28,0x39]
|
||||
vmovapd (%rcx), %zmm7
|
||||
|
||||
// CHECK: vmovapd 291(%rax,%r14,8), %zmm7
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x48,0x28,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovapd 291(%rax,%r14,8), %zmm7
|
||||
|
||||
// CHECK: vmovapd 8128(%rdx), %zmm7
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x28,0x7a,0x7f]
|
||||
vmovapd 8128(%rdx), %zmm7
|
||||
|
||||
// CHECK: vmovapd 8192(%rdx), %zmm7
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x28,0xba,0x00,0x20,0x00,0x00]
|
||||
vmovapd 8192(%rdx), %zmm7
|
||||
|
||||
// CHECK: vmovapd -8192(%rdx), %zmm7
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x28,0x7a,0x80]
|
||||
vmovapd -8192(%rdx), %zmm7
|
||||
|
||||
// CHECK: vmovapd -8256(%rdx), %zmm7
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x28,0xba,0xc0,0xdf,0xff,0xff]
|
||||
vmovapd -8256(%rdx), %zmm7
|
||||
|
||||
// CHECK: vmovaps %zmm9, %zmm5
|
||||
// CHECK: encoding: [0x62,0xd1,0x7c,0x48,0x28,0xe9]
|
||||
vmovaps %zmm9, %zmm5
|
||||
|
||||
// CHECK: vmovaps %zmm9, %zmm5 {%k1}
|
||||
// CHECK: encoding: [0x62,0xd1,0x7c,0x49,0x28,0xe9]
|
||||
vmovaps %zmm9, %zmm5 {%k1}
|
||||
|
||||
// CHECK: vmovaps %zmm9, %zmm5 {%k1} {z}
|
||||
// CHECK: encoding: [0x62,0xd1,0x7c,0xc9,0x28,0xe9]
|
||||
vmovaps %zmm9, %zmm5 {%k1} {z}
|
||||
|
||||
// CHECK: vmovaps (%rcx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7c,0x48,0x28,0x29]
|
||||
vmovaps (%rcx), %zmm5
|
||||
|
||||
// CHECK: vmovaps 291(%rax,%r14,8), %zmm5
|
||||
// CHECK: encoding: [0x62,0xb1,0x7c,0x48,0x28,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovaps 291(%rax,%r14,8), %zmm5
|
||||
|
||||
// CHECK: vmovaps 8128(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7c,0x48,0x28,0x6a,0x7f]
|
||||
vmovaps 8128(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovaps 8192(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7c,0x48,0x28,0xaa,0x00,0x20,0x00,0x00]
|
||||
vmovaps 8192(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovaps -8192(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7c,0x48,0x28,0x6a,0x80]
|
||||
vmovaps -8192(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovaps -8256(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7c,0x48,0x28,0xaa,0xc0,0xdf,0xff,0xff]
|
||||
vmovaps -8256(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x48,0x6f,0xf2]
|
||||
vmovdqa32 %zmm18, %zmm22
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, %zmm22 {%k6}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x4e,0x6f,0xf2]
|
||||
vmovdqa32 %zmm18, %zmm22 {%k6}
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, %zmm22 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0xce,0x6f,0xf2]
|
||||
vmovdqa32 %zmm18, %zmm22 {%k6} {z}
|
||||
|
||||
// CHECK: vmovdqa32 (%rcx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x6f,0x31]
|
||||
vmovdqa32 (%rcx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa32 291(%rax,%r14,8), %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x48,0x6f,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqa32 291(%rax,%r14,8), %zmm22
|
||||
|
||||
// CHECK: vmovdqa32 8128(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x6f,0x72,0x7f]
|
||||
vmovdqa32 8128(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa32 8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x6f,0xb2,0x00,0x20,0x00,0x00]
|
||||
vmovdqa32 8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa32 -8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x6f,0x72,0x80]
|
||||
vmovdqa32 -8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa32 -8256(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x6f,0xb2,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqa32 -8256(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 %zmm12, %zmm22
|
||||
// CHECK: encoding: [0x62,0xc1,0xfd,0x48,0x6f,0xf4]
|
||||
vmovdqa64 %zmm12, %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 %zmm12, %zmm22 {%k5}
|
||||
// CHECK: encoding: [0x62,0xc1,0xfd,0x4d,0x6f,0xf4]
|
||||
vmovdqa64 %zmm12, %zmm22 {%k5}
|
||||
|
||||
// CHECK: vmovdqa64 %zmm12, %zmm22 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0xc1,0xfd,0xcd,0x6f,0xf4]
|
||||
vmovdqa64 %zmm12, %zmm22 {%k5} {z}
|
||||
|
||||
// CHECK: vmovdqa64 (%rcx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x6f,0x31]
|
||||
vmovdqa64 (%rcx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 291(%rax,%r14,8), %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x6f,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqa64 291(%rax,%r14,8), %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 8128(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x6f,0x72,0x7f]
|
||||
vmovdqa64 8128(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x6f,0xb2,0x00,0x20,0x00,0x00]
|
||||
vmovdqa64 8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 -8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x6f,0x72,0x80]
|
||||
vmovdqa64 -8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqa64 -8256(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x6f,0xb2,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqa64 -8256(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovdqu32 %zmm24, %zmm5
|
||||
// CHECK: encoding: [0x62,0x91,0x7e,0x48,0x6f,0xe8]
|
||||
vmovdqu32 %zmm24, %zmm5
|
||||
|
||||
// CHECK: vmovdqu32 %zmm24, %zmm5 {%k5}
|
||||
// CHECK: encoding: [0x62,0x91,0x7e,0x4d,0x6f,0xe8]
|
||||
vmovdqu32 %zmm24, %zmm5 {%k5}
|
||||
|
||||
// CHECK: vmovdqu32 %zmm24, %zmm5 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0x91,0x7e,0xcd,0x6f,0xe8]
|
||||
vmovdqu32 %zmm24, %zmm5 {%k5} {z}
|
||||
|
||||
// CHECK: vmovdqu32 (%rcx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7e,0x48,0x6f,0x29]
|
||||
vmovdqu32 (%rcx), %zmm5
|
||||
|
||||
// CHECK: vmovdqu32 291(%rax,%r14,8), %zmm5
|
||||
// CHECK: encoding: [0x62,0xb1,0x7e,0x48,0x6f,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu32 291(%rax,%r14,8), %zmm5
|
||||
|
||||
// CHECK: vmovdqu32 8128(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7e,0x48,0x6f,0x6a,0x7f]
|
||||
vmovdqu32 8128(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovdqu32 8192(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7e,0x48,0x6f,0xaa,0x00,0x20,0x00,0x00]
|
||||
vmovdqu32 8192(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovdqu32 -8192(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7e,0x48,0x6f,0x6a,0x80]
|
||||
vmovdqu32 -8192(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovdqu32 -8256(%rdx), %zmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x7e,0x48,0x6f,0xaa,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu32 -8256(%rdx), %zmm5
|
||||
|
||||
// CHECK: vmovdqu64 %zmm15, %zmm6
|
||||
// CHECK: encoding: [0x62,0xd1,0xfe,0x48,0x6f,0xf7]
|
||||
vmovdqu64 %zmm15, %zmm6
|
||||
|
||||
// CHECK: vmovdqu64 %zmm15, %zmm6 {%k3}
|
||||
// CHECK: encoding: [0x62,0xd1,0xfe,0x4b,0x6f,0xf7]
|
||||
vmovdqu64 %zmm15, %zmm6 {%k3}
|
||||
|
||||
// CHECK: vmovdqu64 %zmm15, %zmm6 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0xd1,0xfe,0xcb,0x6f,0xf7]
|
||||
vmovdqu64 %zmm15, %zmm6 {%k3} {z}
|
||||
|
||||
// CHECK: vmovdqu64 (%rcx), %zmm6
|
||||
// CHECK: encoding: [0x62,0xf1,0xfe,0x48,0x6f,0x31]
|
||||
vmovdqu64 (%rcx), %zmm6
|
||||
|
||||
// CHECK: vmovdqu64 291(%rax,%r14,8), %zmm6
|
||||
// CHECK: encoding: [0x62,0xb1,0xfe,0x48,0x6f,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu64 291(%rax,%r14,8), %zmm6
|
||||
|
||||
// CHECK: vmovdqu64 8128(%rdx), %zmm6
|
||||
// CHECK: encoding: [0x62,0xf1,0xfe,0x48,0x6f,0x72,0x7f]
|
||||
vmovdqu64 8128(%rdx), %zmm6
|
||||
|
||||
// CHECK: vmovdqu64 8192(%rdx), %zmm6
|
||||
// CHECK: encoding: [0x62,0xf1,0xfe,0x48,0x6f,0xb2,0x00,0x20,0x00,0x00]
|
||||
vmovdqu64 8192(%rdx), %zmm6
|
||||
|
||||
// CHECK: vmovdqu64 -8192(%rdx), %zmm6
|
||||
// CHECK: encoding: [0x62,0xf1,0xfe,0x48,0x6f,0x72,0x80]
|
||||
vmovdqu64 -8192(%rdx), %zmm6
|
||||
|
||||
// CHECK: vmovdqu64 -8256(%rdx), %zmm6
|
||||
// CHECK: encoding: [0x62,0xf1,0xfe,0x48,0x6f,0xb2,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu64 -8256(%rdx), %zmm6
|
||||
|
||||
// CHECK: vmovupd %zmm9, %zmm27
|
||||
// CHECK: encoding: [0x62,0x41,0xfd,0x48,0x10,0xd9]
|
||||
vmovupd %zmm9, %zmm27
|
||||
|
||||
// CHECK: vmovupd %zmm9, %zmm27 {%k2}
|
||||
// CHECK: encoding: [0x62,0x41,0xfd,0x4a,0x10,0xd9]
|
||||
vmovupd %zmm9, %zmm27 {%k2}
|
||||
|
||||
// CHECK: vmovupd %zmm9, %zmm27 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0x41,0xfd,0xca,0x10,0xd9]
|
||||
vmovupd %zmm9, %zmm27 {%k2} {z}
|
||||
|
||||
// CHECK: vmovupd (%rcx), %zmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x48,0x10,0x19]
|
||||
vmovupd (%rcx), %zmm27
|
||||
|
||||
// CHECK: vmovupd 291(%rax,%r14,8), %zmm27
|
||||
// CHECK: encoding: [0x62,0x21,0xfd,0x48,0x10,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovupd 291(%rax,%r14,8), %zmm27
|
||||
|
||||
// CHECK: vmovupd 8128(%rdx), %zmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x48,0x10,0x5a,0x7f]
|
||||
vmovupd 8128(%rdx), %zmm27
|
||||
|
||||
// CHECK: vmovupd 8192(%rdx), %zmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x48,0x10,0x9a,0x00,0x20,0x00,0x00]
|
||||
vmovupd 8192(%rdx), %zmm27
|
||||
|
||||
// CHECK: vmovupd -8192(%rdx), %zmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x48,0x10,0x5a,0x80]
|
||||
vmovupd -8192(%rdx), %zmm27
|
||||
|
||||
// CHECK: vmovupd -8256(%rdx), %zmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x48,0x10,0x9a,0xc0,0xdf,0xff,0xff]
|
||||
vmovupd -8256(%rdx), %zmm27
|
||||
|
||||
// CHECK: vmovups %zmm22, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0x7c,0x48,0x10,0xf6]
|
||||
vmovups %zmm22, %zmm22
|
||||
|
||||
// CHECK: vmovups %zmm22, %zmm22 {%k3}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7c,0x4b,0x10,0xf6]
|
||||
vmovups %zmm22, %zmm22 {%k3}
|
||||
|
||||
// CHECK: vmovups %zmm22, %zmm22 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7c,0xcb,0x10,0xf6]
|
||||
vmovups %zmm22, %zmm22 {%k3} {z}
|
||||
|
||||
// CHECK: vmovups (%rcx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x48,0x10,0x31]
|
||||
vmovups (%rcx), %zmm22
|
||||
|
||||
// CHECK: vmovups 291(%rax,%r14,8), %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0x7c,0x48,0x10,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovups 291(%rax,%r14,8), %zmm22
|
||||
|
||||
// CHECK: vmovups 8128(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x48,0x10,0x72,0x7f]
|
||||
vmovups 8128(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovups 8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x48,0x10,0xb2,0x00,0x20,0x00,0x00]
|
||||
vmovups 8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovups -8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x48,0x10,0x72,0x80]
|
||||
vmovups -8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmovups -8256(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x48,0x10,0xb2,0xc0,0xdf,0xff,0xff]
|
||||
vmovups -8256(%rdx), %zmm22
|
||||
|
||||
// CHECK: vmulpd %zmm23, %zmm4, %zmm24
|
||||
// CHECK: encoding: [0x62,0x21,0xdd,0x48,0x59,0xc7]
|
||||
vmulpd %zmm23, %zmm4, %zmm24
|
||||
@ -2557,6 +2845,230 @@
|
||||
// CHECK: encoding: [0xc5,0x78,0x93,0xea]
|
||||
kmovw %k2, %r13d
|
||||
|
||||
// CHECK: vmovapd %zmm18, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x29,0x11]
|
||||
vmovapd %zmm18, (%rcx)
|
||||
|
||||
// CHECK: vmovapd %zmm18, (%rcx) {%k6}
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x4e,0x29,0x11]
|
||||
vmovapd %zmm18, (%rcx) {%k6}
|
||||
|
||||
// CHECK: vmovapd %zmm18, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x29,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovapd %zmm18, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovapd %zmm18, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x29,0x52,0x7f]
|
||||
vmovapd %zmm18, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovapd %zmm18, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x29,0x92,0x00,0x20,0x00,0x00]
|
||||
vmovapd %zmm18, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovapd %zmm18, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x29,0x52,0x80]
|
||||
vmovapd %zmm18, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovapd %zmm18, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x29,0x92,0xc0,0xdf,0xff,0xff]
|
||||
vmovapd %zmm18, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovaps %zmm9, (%rcx)
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x29,0x09]
|
||||
vmovaps %zmm9, (%rcx)
|
||||
|
||||
// CHECK: vmovaps %zmm9, (%rcx) {%k3}
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x4b,0x29,0x09]
|
||||
vmovaps %zmm9, (%rcx) {%k3}
|
||||
|
||||
// CHECK: vmovaps %zmm9, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0x31,0x7c,0x48,0x29,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovaps %zmm9, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovaps %zmm9, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x29,0x4a,0x7f]
|
||||
vmovaps %zmm9, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovaps %zmm9, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x29,0x8a,0x00,0x20,0x00,0x00]
|
||||
vmovaps %zmm9, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovaps %zmm9, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x29,0x4a,0x80]
|
||||
vmovaps %zmm9, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovaps %zmm9, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x29,0x8a,0xc0,0xdf,0xff,0xff]
|
||||
vmovaps %zmm9, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7f,0x11]
|
||||
vmovdqa32 %zmm18, (%rcx)
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, (%rcx) {%k4}
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x4c,0x7f,0x11]
|
||||
vmovdqa32 %zmm18, (%rcx) {%k4}
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x48,0x7f,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqa32 %zmm18, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7f,0x52,0x7f]
|
||||
vmovdqa32 %zmm18, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7f,0x92,0x00,0x20,0x00,0x00]
|
||||
vmovdqa32 %zmm18, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7f,0x52,0x80]
|
||||
vmovdqa32 %zmm18, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqa32 %zmm18, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7f,0x92,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqa32 %zmm18, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7f,0x19]
|
||||
vmovdqa64 %zmm19, (%rcx)
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, (%rcx) {%k5}
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x4d,0x7f,0x19]
|
||||
vmovdqa64 %zmm19, (%rcx) {%k5}
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x7f,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqa64 %zmm19, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7f,0x5a,0x7f]
|
||||
vmovdqa64 %zmm19, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7f,0x9a,0x00,0x20,0x00,0x00]
|
||||
vmovdqa64 %zmm19, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7f,0x5a,0x80]
|
||||
vmovdqa64 %zmm19, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqa64 %zmm19, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7f,0x9a,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqa64 %zmm19, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x7f,0x31]
|
||||
vmovdqu32 %zmm22, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, (%rcx) {%k1}
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x49,0x7f,0x31]
|
||||
vmovdqu32 %zmm22, (%rcx) {%k1}
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x48,0x7f,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu32 %zmm22, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x7f,0x72,0x7f]
|
||||
vmovdqu32 %zmm22, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x7f,0xb2,0x00,0x20,0x00,0x00]
|
||||
vmovdqu32 %zmm22, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x7f,0x72,0x80]
|
||||
vmovdqu32 %zmm22, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu32 %zmm22, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x7f,0xb2,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu32 %zmm22, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, (%rcx)
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x48,0x7f,0x01]
|
||||
vmovdqu64 %zmm24, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, (%rcx) {%k5}
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x4d,0x7f,0x01]
|
||||
vmovdqu64 %zmm24, (%rcx) {%k5}
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0x21,0xfe,0x48,0x7f,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu64 %zmm24, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x48,0x7f,0x42,0x7f]
|
||||
vmovdqu64 %zmm24, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x48,0x7f,0x82,0x00,0x20,0x00,0x00]
|
||||
vmovdqu64 %zmm24, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x48,0x7f,0x42,0x80]
|
||||
vmovdqu64 %zmm24, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu64 %zmm24, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x48,0x7f,0x82,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu64 %zmm24, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovupd %zmm10, (%rcx)
|
||||
// CHECK: encoding: [0x62,0x71,0xfd,0x48,0x11,0x11]
|
||||
vmovupd %zmm10, (%rcx)
|
||||
|
||||
// CHECK: vmovupd %zmm10, (%rcx) {%k7}
|
||||
// CHECK: encoding: [0x62,0x71,0xfd,0x4f,0x11,0x11]
|
||||
vmovupd %zmm10, (%rcx) {%k7}
|
||||
|
||||
// CHECK: vmovupd %zmm10, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0x31,0xfd,0x48,0x11,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovupd %zmm10, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovupd %zmm10, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0xfd,0x48,0x11,0x52,0x7f]
|
||||
vmovupd %zmm10, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovupd %zmm10, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0xfd,0x48,0x11,0x92,0x00,0x20,0x00,0x00]
|
||||
vmovupd %zmm10, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovupd %zmm10, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0xfd,0x48,0x11,0x52,0x80]
|
||||
vmovupd %zmm10, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovupd %zmm10, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0x71,0xfd,0x48,0x11,0x92,0xc0,0xdf,0xff,0xff]
|
||||
vmovupd %zmm10, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovups %zmm24, (%rcx)
|
||||
// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x11,0x01]
|
||||
vmovups %zmm24, (%rcx)
|
||||
|
||||
// CHECK: vmovups %zmm24, (%rcx) {%k7}
|
||||
// CHECK: encoding: [0x62,0x61,0x7c,0x4f,0x11,0x01]
|
||||
vmovups %zmm24, (%rcx) {%k7}
|
||||
|
||||
// CHECK: vmovups %zmm24, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0x21,0x7c,0x48,0x11,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovups %zmm24, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovups %zmm24, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x11,0x42,0x7f]
|
||||
vmovups %zmm24, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovups %zmm24, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x11,0x82,0x00,0x20,0x00,0x00]
|
||||
vmovups %zmm24, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovups %zmm24, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x11,0x42,0x80]
|
||||
vmovups %zmm24, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovups %zmm24, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x11,0x82,0xc0,0xdf,0xff,0xff]
|
||||
vmovups %zmm24, -8256(%rdx)
|
||||
|
||||
// CHECK: vpmovqb %zmm2, %xmm3
|
||||
// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0xd3]
|
||||
vpmovqb %zmm2, %xmm3
|
||||
|
||||
@ -1,5 +1,77 @@
|
||||
// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=skx --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vmovdqu8 %zmm19, %zmm29
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x48,0x6f,0xeb]
|
||||
vmovdqu8 %zmm19, %zmm29
|
||||
|
||||
// CHECK: vmovdqu8 %zmm19, %zmm29 {%k7}
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x4f,0x6f,0xeb]
|
||||
vmovdqu8 %zmm19, %zmm29 {%k7}
|
||||
|
||||
// CHECK: vmovdqu8 %zmm19, %zmm29 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0xcf,0x6f,0xeb]
|
||||
vmovdqu8 %zmm19, %zmm29 {%k7} {z}
|
||||
|
||||
// CHECK: vmovdqu8 (%rcx), %zmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x48,0x6f,0x29]
|
||||
vmovdqu8 (%rcx), %zmm29
|
||||
|
||||
// CHECK: vmovdqu8 291(%rax,%r14,8), %zmm29
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x48,0x6f,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu8 291(%rax,%r14,8), %zmm29
|
||||
|
||||
// CHECK: vmovdqu8 8128(%rdx), %zmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x48,0x6f,0x6a,0x7f]
|
||||
vmovdqu8 8128(%rdx), %zmm29
|
||||
|
||||
// CHECK: vmovdqu8 8192(%rdx), %zmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x48,0x6f,0xaa,0x00,0x20,0x00,0x00]
|
||||
vmovdqu8 8192(%rdx), %zmm29
|
||||
|
||||
// CHECK: vmovdqu8 -8192(%rdx), %zmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x48,0x6f,0x6a,0x80]
|
||||
vmovdqu8 -8192(%rdx), %zmm29
|
||||
|
||||
// CHECK: vmovdqu8 -8256(%rdx), %zmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x48,0x6f,0xaa,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu8 -8256(%rdx), %zmm29
|
||||
|
||||
// CHECK: vmovdqu16 %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x48,0x6f,0xca]
|
||||
vmovdqu16 %zmm18, %zmm17
|
||||
|
||||
// CHECK: vmovdqu16 %zmm18, %zmm17 {%k3}
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x4b,0x6f,0xca]
|
||||
vmovdqu16 %zmm18, %zmm17 {%k3}
|
||||
|
||||
// CHECK: vmovdqu16 %zmm18, %zmm17 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0xcb,0x6f,0xca]
|
||||
vmovdqu16 %zmm18, %zmm17 {%k3} {z}
|
||||
|
||||
// CHECK: vmovdqu16 (%rcx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x48,0x6f,0x09]
|
||||
vmovdqu16 (%rcx), %zmm17
|
||||
|
||||
// CHECK: vmovdqu16 291(%rax,%r14,8), %zmm17
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x48,0x6f,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu16 291(%rax,%r14,8), %zmm17
|
||||
|
||||
// CHECK: vmovdqu16 8128(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x48,0x6f,0x4a,0x7f]
|
||||
vmovdqu16 8128(%rdx), %zmm17
|
||||
|
||||
// CHECK: vmovdqu16 8192(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x48,0x6f,0x8a,0x00,0x20,0x00,0x00]
|
||||
vmovdqu16 8192(%rdx), %zmm17
|
||||
|
||||
// CHECK: vmovdqu16 -8192(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x48,0x6f,0x4a,0x80]
|
||||
vmovdqu16 -8192(%rdx), %zmm17
|
||||
|
||||
// CHECK: vmovdqu16 -8256(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x48,0x6f,0x8a,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu16 -8256(%rdx), %zmm17
|
||||
|
||||
// CHECK: kandq %k7, %k5, %k5
|
||||
// CHECK: encoding: [0xc4,0xe1,0xd4,0x41,0xef]
|
||||
kandq %k7, %k5, %k5
|
||||
@ -127,3 +199,59 @@
|
||||
// CHECK: kmovd %k5, %r13d
|
||||
// CHECK: encoding: [0xc5,0x7b,0x93,0xed]
|
||||
kmovd %k5, %r13d
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x48,0x7f,0x11]
|
||||
vmovdqu8 %zmm18, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, (%rcx) {%k3}
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x4b,0x7f,0x11]
|
||||
vmovdqu8 %zmm18, (%rcx) {%k3}
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0x7f,0x48,0x7f,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu8 %zmm18, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x48,0x7f,0x52,0x7f]
|
||||
vmovdqu8 %zmm18, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x48,0x7f,0x92,0x00,0x20,0x00,0x00]
|
||||
vmovdqu8 %zmm18, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x48,0x7f,0x52,0x80]
|
||||
vmovdqu8 %zmm18, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %zmm18, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x48,0x7f,0x92,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu8 %zmm18, -8256(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, (%rcx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x48,0x7f,0x21]
|
||||
vmovdqu16 %zmm28, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, (%rcx) {%k6}
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x4e,0x7f,0x21]
|
||||
vmovdqu16 %zmm28, (%rcx) {%k6}
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0x21,0xff,0x48,0x7f,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu16 %zmm28, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, 8128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x48,0x7f,0x62,0x7f]
|
||||
vmovdqu16 %zmm28, 8128(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, 8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x48,0x7f,0xa2,0x00,0x20,0x00,0x00]
|
||||
vmovdqu16 %zmm28, 8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, -8192(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x48,0x7f,0x62,0x80]
|
||||
vmovdqu16 %zmm28, -8192(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %zmm28, -8256(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x48,0x7f,0xa2,0xc0,0xdf,0xff,0xff]
|
||||
vmovdqu16 %zmm28, -8256(%rdx)
|
||||
|
||||
257
test/MC/X86/x86-64-avx512bw_vl.s
Normal file
257
test/MC/X86/x86-64-avx512bw_vl.s
Normal file
@ -0,0 +1,257 @@
|
||||
// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=skx --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vmovdqu8 %xmm23, %xmm26
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x08,0x6f,0xd7]
|
||||
vmovdqu8 %xmm23, %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 %xmm23, %xmm26 {%k2}
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x0a,0x6f,0xd7]
|
||||
vmovdqu8 %xmm23, %xmm26 {%k2}
|
||||
|
||||
// CHECK: vmovdqu8 %xmm23, %xmm26 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x8a,0x6f,0xd7]
|
||||
vmovdqu8 %xmm23, %xmm26 {%k2} {z}
|
||||
|
||||
// CHECK: vmovdqu8 (%rcx), %xmm26
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x08,0x6f,0x11]
|
||||
vmovdqu8 (%rcx), %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 291(%rax,%r14,8), %xmm26
|
||||
// CHECK: encoding: [0x62,0x21,0x7f,0x08,0x6f,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu8 291(%rax,%r14,8), %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 2032(%rdx), %xmm26
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x08,0x6f,0x52,0x7f]
|
||||
vmovdqu8 2032(%rdx), %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 2048(%rdx), %xmm26
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x08,0x6f,0x92,0x00,0x08,0x00,0x00]
|
||||
vmovdqu8 2048(%rdx), %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 -2048(%rdx), %xmm26
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x08,0x6f,0x52,0x80]
|
||||
vmovdqu8 -2048(%rdx), %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 -2064(%rdx), %xmm26
|
||||
// CHECK: encoding: [0x62,0x61,0x7f,0x08,0x6f,0x92,0xf0,0xf7,0xff,0xff]
|
||||
vmovdqu8 -2064(%rdx), %xmm26
|
||||
|
||||
// CHECK: vmovdqu8 %ymm29, %ymm18
|
||||
// CHECK: encoding: [0x62,0x81,0x7f,0x28,0x6f,0xd5]
|
||||
vmovdqu8 %ymm29, %ymm18
|
||||
|
||||
// CHECK: vmovdqu8 %ymm29, %ymm18 {%k7}
|
||||
// CHECK: encoding: [0x62,0x81,0x7f,0x2f,0x6f,0xd5]
|
||||
vmovdqu8 %ymm29, %ymm18 {%k7}
|
||||
|
||||
// CHECK: vmovdqu8 %ymm29, %ymm18 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x7f,0xaf,0x6f,0xd5]
|
||||
vmovdqu8 %ymm29, %ymm18 {%k7} {z}
|
||||
|
||||
// CHECK: vmovdqu8 (%rcx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x6f,0x11]
|
||||
vmovdqu8 (%rcx), %ymm18
|
||||
|
||||
// CHECK: vmovdqu8 291(%rax,%r14,8), %ymm18
|
||||
// CHECK: encoding: [0x62,0xa1,0x7f,0x28,0x6f,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu8 291(%rax,%r14,8), %ymm18
|
||||
|
||||
// CHECK: vmovdqu8 4064(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x6f,0x52,0x7f]
|
||||
vmovdqu8 4064(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovdqu8 4096(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x6f,0x92,0x00,0x10,0x00,0x00]
|
||||
vmovdqu8 4096(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovdqu8 -4096(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x6f,0x52,0x80]
|
||||
vmovdqu8 -4096(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovdqu8 -4128(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x6f,0x92,0xe0,0xef,0xff,0xff]
|
||||
vmovdqu8 -4128(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovdqu16 %xmm24, %xmm29
|
||||
// CHECK: encoding: [0x62,0x01,0xff,0x08,0x6f,0xe8]
|
||||
vmovdqu16 %xmm24, %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 %xmm24, %xmm29 {%k6}
|
||||
// CHECK: encoding: [0x62,0x01,0xff,0x0e,0x6f,0xe8]
|
||||
vmovdqu16 %xmm24, %xmm29 {%k6}
|
||||
|
||||
// CHECK: vmovdqu16 %xmm24, %xmm29 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0xff,0x8e,0x6f,0xe8]
|
||||
vmovdqu16 %xmm24, %xmm29 {%k6} {z}
|
||||
|
||||
// CHECK: vmovdqu16 (%rcx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x08,0x6f,0x29]
|
||||
vmovdqu16 (%rcx), %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 291(%rax,%r14,8), %xmm29
|
||||
// CHECK: encoding: [0x62,0x21,0xff,0x08,0x6f,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu16 291(%rax,%r14,8), %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 2032(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x08,0x6f,0x6a,0x7f]
|
||||
vmovdqu16 2032(%rdx), %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 2048(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x08,0x6f,0xaa,0x00,0x08,0x00,0x00]
|
||||
vmovdqu16 2048(%rdx), %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 -2048(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x08,0x6f,0x6a,0x80]
|
||||
vmovdqu16 -2048(%rdx), %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 -2064(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x08,0x6f,0xaa,0xf0,0xf7,0xff,0xff]
|
||||
vmovdqu16 -2064(%rdx), %xmm29
|
||||
|
||||
// CHECK: vmovdqu16 %ymm24, %ymm23
|
||||
// CHECK: encoding: [0x62,0x81,0xff,0x28,0x6f,0xf8]
|
||||
vmovdqu16 %ymm24, %ymm23
|
||||
|
||||
// CHECK: vmovdqu16 %ymm24, %ymm23 {%k3}
|
||||
// CHECK: encoding: [0x62,0x81,0xff,0x2b,0x6f,0xf8]
|
||||
vmovdqu16 %ymm24, %ymm23 {%k3}
|
||||
|
||||
// CHECK: vmovdqu16 %ymm24, %ymm23 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xff,0xab,0x6f,0xf8]
|
||||
vmovdqu16 %ymm24, %ymm23 {%k3} {z}
|
||||
|
||||
// CHECK: vmovdqu16 (%rcx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x6f,0x39]
|
||||
vmovdqu16 (%rcx), %ymm23
|
||||
|
||||
// CHECK: vmovdqu16 291(%rax,%r14,8), %ymm23
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x28,0x6f,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu16 291(%rax,%r14,8), %ymm23
|
||||
|
||||
// CHECK: vmovdqu16 4064(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x6f,0x7a,0x7f]
|
||||
vmovdqu16 4064(%rdx), %ymm23
|
||||
|
||||
// CHECK: vmovdqu16 4096(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x6f,0xba,0x00,0x10,0x00,0x00]
|
||||
vmovdqu16 4096(%rdx), %ymm23
|
||||
|
||||
// CHECK: vmovdqu16 -4096(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x6f,0x7a,0x80]
|
||||
vmovdqu16 -4096(%rdx), %ymm23
|
||||
|
||||
// CHECK: vmovdqu16 -4128(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x6f,0xba,0xe0,0xef,0xff,0xff]
|
||||
vmovdqu16 -4128(%rdx), %ymm23
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x08,0x7f,0x09]
|
||||
vmovdqu8 %xmm17, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, (%rcx) {%k4}
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x0c,0x7f,0x09]
|
||||
vmovdqu8 %xmm17, (%rcx) {%k4}
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0x7f,0x08,0x7f,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu8 %xmm17, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, 2032(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x08,0x7f,0x4a,0x7f]
|
||||
vmovdqu8 %xmm17, 2032(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, 2048(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x08,0x7f,0x8a,0x00,0x08,0x00,0x00]
|
||||
vmovdqu8 %xmm17, 2048(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, -2048(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x08,0x7f,0x4a,0x80]
|
||||
vmovdqu8 %xmm17, -2048(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %xmm17, -2064(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x08,0x7f,0x8a,0xf0,0xf7,0xff,0xff]
|
||||
vmovdqu8 %xmm17, -2064(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x7f,0x29]
|
||||
vmovdqu8 %ymm21, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, (%rcx) {%k1}
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x29,0x7f,0x29]
|
||||
vmovdqu8 %ymm21, (%rcx) {%k1}
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0x7f,0x28,0x7f,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu8 %ymm21, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, 4064(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x7f,0x6a,0x7f]
|
||||
vmovdqu8 %ymm21, 4064(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, 4096(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x7f,0xaa,0x00,0x10,0x00,0x00]
|
||||
vmovdqu8 %ymm21, 4096(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, -4096(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x7f,0x6a,0x80]
|
||||
vmovdqu8 %ymm21, -4096(%rdx)
|
||||
|
||||
// CHECK: vmovdqu8 %ymm21, -4128(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0x7f,0x28,0x7f,0xaa,0xe0,0xef,0xff,0xff]
|
||||
vmovdqu8 %ymm21, -4128(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7f,0x39]
|
||||
vmovdqu16 %xmm23, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, (%rcx) {%k7}
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x0f,0x7f,0x39]
|
||||
vmovdqu16 %xmm23, (%rcx) {%k7}
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x08,0x7f,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu16 %xmm23, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, 2032(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7f,0x7a,0x7f]
|
||||
vmovdqu16 %xmm23, 2032(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, 2048(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7f,0xba,0x00,0x08,0x00,0x00]
|
||||
vmovdqu16 %xmm23, 2048(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, -2048(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7f,0x7a,0x80]
|
||||
vmovdqu16 %xmm23, -2048(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %xmm23, -2064(%rdx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7f,0xba,0xf0,0xf7,0xff,0xff]
|
||||
vmovdqu16 %xmm23, -2064(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, (%rcx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7f,0x29]
|
||||
vmovdqu16 %ymm29, (%rcx)
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, (%rcx) {%k6}
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x2e,0x7f,0x29]
|
||||
vmovdqu16 %ymm29, (%rcx) {%k6}
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, 291(%rax,%r14,8)
|
||||
// CHECK: encoding: [0x62,0x21,0xff,0x28,0x7f,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovdqu16 %ymm29, 291(%rax,%r14,8)
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, 4064(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7f,0x6a,0x7f]
|
||||
vmovdqu16 %ymm29, 4064(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, 4096(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7f,0xaa,0x00,0x10,0x00,0x00]
|
||||
vmovdqu16 %ymm29, 4096(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, -4096(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7f,0x6a,0x80]
|
||||
vmovdqu16 %ymm29, -4096(%rdx)
|
||||
|
||||
// CHECK: vmovdqu16 %ymm29, -4128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7f,0xaa,0xe0,0xef,0xff,0xff]
|
||||
vmovdqu16 %ymm29, -4128(%rdx)
|
||||
1025
test/MC/X86/x86-64-avx512f_vl.s
Normal file
1025
test/MC/X86/x86-64-avx512f_vl.s
Normal file
File diff suppressed because it is too large
Load Diff
@ -205,8 +205,19 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_XD_K:
|
||||
return inheritsFrom(child, IC_EVEX_W_XD_K) ||
|
||||
inheritsFrom(child, IC_EVEX_L_W_XD_K);
|
||||
case IC_EVEX_K_B:
|
||||
case IC_EVEX_KZ:
|
||||
return false;
|
||||
case IC_EVEX_XS_KZ:
|
||||
return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
|
||||
inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
|
||||
case IC_EVEX_XD_KZ:
|
||||
return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
|
||||
inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
|
||||
case IC_EVEX_KZ_B:
|
||||
case IC_EVEX_OPSIZE_K:
|
||||
case IC_EVEX_OPSIZE_B:
|
||||
case IC_EVEX_OPSIZE_KZ:
|
||||
return false;
|
||||
case IC_EVEX_W_K:
|
||||
case IC_EVEX_W_XS_K:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user