diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index eef117af300..01727c38877 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -923,7 +923,6 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
   unsigned NewVReg = 0;
   unsigned index = getBaseIndex(I->start);
   unsigned end = getBaseIndex(I->end-1) + InstrSlots::NUM;
-  bool TrySplitMI = TrySplit && vrm.getPreSplitReg(li.reg) == 0;
   for (; index != end; index += InstrSlots::NUM) {
     // skip deleted instructions
     while (index != end && !getInstructionFromIndex(index))
@@ -933,7 +932,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
     MachineInstr *MI = getInstructionFromIndex(index);
     MachineBasicBlock *MBB = MI->getParent();
     NewVReg = 0;
-    if (TrySplitMI) {
+    if (TrySplit) {
       std::map<unsigned,unsigned>::const_iterator NVI =
         MBBVRegsMap.find(MBB->getNumber());
       if (NVI != MBBVRegsMap.end()) {
@@ -977,7 +976,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
 
     // Update weight of spill interval.
     LiveInterval &nI = getOrCreateInterval(NewVReg);
-    if (!TrySplitMI) {
+    if (!TrySplit) {
       // The spill weight is now infinity as it cannot be spilled again.
       nI.weight = HUGE_VALF;
       continue;
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index a7154b2f063..68c47736738 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -276,7 +276,7 @@ namespace {
                              SmallSet<MachineInstr*, 4> &ReMatDefs,
                              BitVector &RegKills,
                              std::vector<MachineOperand*> &KillOps,
-                             VirtRegMap &VRM);
+                             VirtRegMap &VRM, bool StoreMaybeDead);
     void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
   };
 }
@@ -860,7 +860,7 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
                                   SmallSet<MachineInstr*, 4> &ReMatDefs,
                                   BitVector &RegKills,
                                   std::vector<MachineOperand*> &KillOps,
-                                  VirtRegMap &VRM) {
+                                  VirtRegMap &VRM, bool StoreMaybeDead) {
   MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
   DOUT << "Store:\t" << *next(MII);
 
@@ -896,14 +896,15 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
     }
   }
 
-  LastStore = next(MII);
+  MachineInstr *NewStore = next(MII);
+  LastStore = StoreMaybeDead ? NewStore : NULL;
 
   // If the stack slot value was previously available in some other
   // register, change it now.  Otherwise, make the register available,
   // in PhysReg.
   Spills.ModifyStackSlotOrReMat(StackSlot);
   Spills.ClobberPhysReg(PhysReg);
-  Spills.addAvailable(StackSlot, LastStore, PhysReg);
+  Spills.addAvailable(StackSlot, NewStore, PhysReg);
   ++NumStores;
 }
 
@@ -985,8 +986,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         unsigned Phys = VRM.getPhys(VirtReg);
         int StackSlot = VRM.getStackSlot(VirtReg);
         MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
-        SpillRegToStackSlot(MBB, MII, i, Phys, StackSlot, RC,
-                            LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
+        SpillRegToStackSlot(MBB, MII, i, Phys, StackSlot, RC, LastStore,
+                            Spills, ReMatDefs, RegKills, KillOps, VRM, false);
       }
     }
 
@@ -1009,7 +1010,13 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
       
       assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
              "Not a virtual or a physical register?");
-      
+
+      // Assumes this is the last use of a split interval. IsKill will be unset
+      // if reg is use later unless it's a two-address operand.
+      if (MO.isUse() && VRM.getPreSplitReg(VirtReg) &&
+          TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
+        MI.getOperand(i).setIsKill();
+
       unsigned SubIdx = MO.getSubReg();
       if (VRM.isAssignedReg(VirtReg)) {
         // This virtual register was assigned a physreg!
@@ -1440,7 +1447,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
       if (!MO.isDead()) {
         MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
         SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, LastStore,
-                            Spills, ReMatDefs, RegKills, KillOps, VRM);
+                            Spills, ReMatDefs, RegKills, KillOps, VRM, true);
 
         // Check to see if this is a noop copy.  If so, eliminate the
         // instruction before considering the dest reg to be changed.