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ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
c5a8c861c9
commit
7032741e7b
@ -1011,56 +1011,30 @@ class AI_ext_rrot_np<bits<8> opcod, string opc>
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/// AI_exta_rrot - A binary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
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Requires<[IsARM, HasV6]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<4> Rn;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-10} = 0b00;
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let Inst{9-4} = 0b000111;
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let Inst{3-0} = Rm;
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}
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def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
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rot_imm:$rot),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
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[(set GPR:$Rd, (opnode GPR:$Rn,
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(rotr GPR:$Rm, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<4> Rn;
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bits<2> rot;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-10} = rot;
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let Inst{9-4} = 0b000111;
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let Inst{3-0} = Rm;
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}
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class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
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: AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
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[(set GPR:$Rd, (opnode GPR:$Rn, (rotr GPR:$Rm, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<4> Rn;
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bits<2> rot;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-10} = rot;
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let Inst{9-4} = 0b000111;
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let Inst{3-0} = Rm;
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}
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// For disassembly only.
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multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
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def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV6]> {
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let Inst{11-10} = 0b00;
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}
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def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
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rot_imm:$rot),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV6]> {
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bits<4> Rn;
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bits<2> rot;
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let Inst{19-16} = Rn;
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let Inst{11-10} = rot;
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}
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class AI_exta_rrot_np<bits<8> opcod, string opc>
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: AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
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Requires<[IsARM, HasV6]> {
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bits<4> Rn;
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bits<2> rot;
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let Inst{19-16} = Rn;
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let Inst{11-10} = rot;
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}
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/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
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@ -2377,14 +2351,14 @@ def SXTB : AI_ext_rrot<0b01101010,
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def SXTH : AI_ext_rrot<0b01101011,
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"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
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defm SXTAB : AI_exta_rrot<0b01101010,
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def SXTAB : AI_exta_rrot<0b01101010,
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"sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
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defm SXTAH : AI_exta_rrot<0b01101011,
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def SXTAH : AI_exta_rrot<0b01101011,
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"sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
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def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
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defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
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def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
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// Zero extenders
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@ -2405,15 +2379,14 @@ def UXTB16 : AI_ext_rrot<0b01101100,
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def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
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(UXTB16 GPR:$Src, 1)>;
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defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
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def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
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BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
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defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
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def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
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BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
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}
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// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
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// For disassembly only
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defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
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def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
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def SBFX : I<(outs GPR:$Rd),
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@ -4265,14 +4238,24 @@ def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
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Requires<[IsARM, HasV6]>;
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// SXT/UXT with no rotate
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let AddedComplexity = 16 in {
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def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
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def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
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let AddedComplexity = 10 in
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def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
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def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
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(UXTAB GPR:$Rn, GPR:$Rm, 0)>;
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def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
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(UXTAH GPR:$Rn, GPR:$Rm, 0)>;
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}
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def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
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def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
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def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i8)),
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(SXTAB GPR:$Rn, GPR:$Rm, 0)>;
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def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i16)),
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(SXTAH GPR:$Rn, GPR:$Rm, 0)>;
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//===----------------------------------------------------------------------===//
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// Thumb Support
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//
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@ -993,116 +993,64 @@ class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
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}
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// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
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multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
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def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
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opc, "\t$Rd, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
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IIC_iEXTr, opc, "\t$dst, $Rm$rot",
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[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
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: T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
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IIC_iEXTr, opc, "\t$dst, $Rm$rot",
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[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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bits<2> rot;
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = rot;
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}
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// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
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// supported yet.
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multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
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def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
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opc, "\t$Rd, $Rm", []>,
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class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
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: T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
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opc, "\t$Rd, $Rm$rot", []>,
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Requires<[IsThumb2, HasT2ExtractPack]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
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opc, "\t$Rd, $Rm, ror $rot", []>,
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Requires<[IsThumb2, HasT2ExtractPack]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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bits<2> rot;
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = rot;
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}
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/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
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opc, "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
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(ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
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IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
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[(set rGPR:$Rd, (opnode rGPR:$Rn,
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(rotr rGPR:$Rm, rot_imm:$rot)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
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: T2ThreeReg<(outs rGPR:$Rd),
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(ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
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IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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bits<2> rot;
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = rot;
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}
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multiclass T2I_exta_rrot_np<bits<3> opcod, string opc> {
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
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opc, "\t$Rd, $Rn, $Rm", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
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IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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class T2I_exta_rrot_np<bits<3> opcod, string opc>
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: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
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IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
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bits<2> rot;
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = rot;
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}
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//===----------------------------------------------------------------------===//
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@ -1661,15 +1609,15 @@ def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
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UnOpFrag<(sext_inreg node:$Src, i8)>>;
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def t2SXTH : T2I_ext_rrot<0b000, "sxth",
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UnOpFrag<(sext_inreg node:$Src, i16)>>;
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defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
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def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
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defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
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def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
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BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
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defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
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def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
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BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
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defm t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
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def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
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// TODO: SXT(A){B|H}16 - done for disassembly only
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// TODO: SXT(A){B|H}16
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// Zero extenders
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@ -1678,7 +1626,7 @@ def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
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UnOpFrag<(and node:$Src, 0x000000FF)>>;
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def t2UXTH : T2I_ext_rrot<0b001, "uxth",
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UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
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defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
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||||
def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
|
||||
UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
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||||
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||||
// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
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||||
@ -1686,17 +1634,17 @@ defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
|
||||
// instead so we can include a check for masking back in the upper
|
||||
// eight bits of the source into the lower eight bits of the result.
|
||||
//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
|
||||
// (t2UXTB16r_rot rGPR:$Src, 3)>,
|
||||
// (t2UXTB16 rGPR:$Src, 3)>,
|
||||
// Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
|
||||
(t2UXTB16r_rot rGPR:$Src, 1)>,
|
||||
(t2UXTB16 rGPR:$Src, 1)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
|
||||
defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
|
||||
def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
|
||||
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
|
||||
defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
|
||||
def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
|
||||
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
|
||||
defm t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
|
||||
def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -3458,8 +3406,28 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
|
||||
//
|
||||
|
||||
// SXT/UXT with no rotate
|
||||
def : T2Pat<(and rGPR:$Src, 0x000000FF), (t2UXTB rGPR:$Src, 0)>;
|
||||
def : T2Pat<(and rGPR:$Src, 0x0000FFFF), (t2UXTH rGPR:$Src, 0)>;
|
||||
let AddedComplexity = 16 in {
|
||||
def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
|
||||
(t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
|
||||
(t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
}
|
||||
|
||||
def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>;
|
||||
def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>;
|
||||
def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
|
||||
(t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
|
||||
(t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user