mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
Convert DOUT to DEBUG(errs()...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79765 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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52283486bc
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@ -181,13 +181,18 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
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*tri_->getSubRegisters(IntB.reg)) {
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*tri_->getSubRegisters(IntB.reg)) {
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for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
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for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
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if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
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if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
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DOUT << "Interfere with sub-register ";
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DEBUG({
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DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
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errs() << "Interfere with sub-register ";
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li_->getInterval(*SR).print(errs(), tri_);
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});
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return false;
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return false;
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}
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}
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}
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}
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DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
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DEBUG({
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errs() << "\nExtending: ";
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IntB.print(errs(), tri_);
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});
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unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
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unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
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// We are about to delete CopyMI, so need to remove it as the 'instruction
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// We are about to delete CopyMI, so need to remove it as the 'instruction
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@ -217,8 +222,11 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
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IntB.addKills(ValLR->valno, BValNo->kills);
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IntB.addKills(ValLR->valno, BValNo->kills);
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IntB.MergeValueNumberInto(BValNo, ValLR->valno);
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IntB.MergeValueNumberInto(BValNo, ValLR->valno);
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}
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}
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DOUT << " result = "; IntB.print(DOUT, tri_);
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DEBUG({
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DOUT << "\n";
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errs() << " result = ";
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IntB.print(errs(), tri_);
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errs() << "\n";
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});
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// If the source instruction was killing the source register before the
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// If the source instruction was killing the source register before the
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// merge, unset the isKill marker given the live range has been extended.
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// merge, unset the isKill marker given the live range has been extended.
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@ -444,7 +452,10 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
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// We need to insert a new liverange: [ALR.start, LastUse). It may be we can
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// We need to insert a new liverange: [ALR.start, LastUse). It may be we can
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// simply extend BLR if CopyMI doesn't end the range.
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// simply extend BLR if CopyMI doesn't end the range.
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DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
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DEBUG({
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errs() << "\nExtending: ";
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IntB.print(errs(), tri_);
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});
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// Remove val#'s defined by copies that will be coalesced away.
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// Remove val#'s defined by copies that will be coalesced away.
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for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
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for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
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@ -491,13 +502,21 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
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IntB.addKills(ValNo, BKills);
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IntB.addKills(ValNo, BKills);
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ValNo->setHasPHIKill(BHasPHIKill);
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ValNo->setHasPHIKill(BHasPHIKill);
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DOUT << " result = "; IntB.print(DOUT, tri_);
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DEBUG({
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DOUT << "\n";
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errs() << " result = ";
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IntB.print(errs(), tri_);
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errs() << '\n';
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errs() << "\nShortening: ";
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IntA.print(errs(), tri_);
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});
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DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
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IntA.removeValNo(AValNo);
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IntA.removeValNo(AValNo);
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DOUT << " result = "; IntA.print(DOUT, tri_);
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DOUT << "\n";
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DEBUG({
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errs() << " result = ";
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IntA.print(errs(), tri_);
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errs() << '\n';
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});
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++numCommutes;
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++numCommutes;
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return true;
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return true;
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@ -1185,14 +1204,18 @@ SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
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LiveInterval &RHS = li_->getInterval(SrcReg);
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LiveInterval &RHS = li_->getInterval(SrcReg);
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if (li_->hasInterval(RealDstReg) &&
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if (li_->hasInterval(RealDstReg) &&
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RHS.overlaps(li_->getInterval(RealDstReg))) {
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RHS.overlaps(li_->getInterval(RealDstReg))) {
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DOUT << "Interfere with register ";
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DEBUG({
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DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
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errs() << "Interfere with register ";
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li_->getInterval(RealDstReg).print(errs(), tri_);
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});
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return false; // Not coalescable
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return false; // Not coalescable
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}
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}
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for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
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for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
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if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
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if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
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DOUT << "Interfere with sub-register ";
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DEBUG({
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DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
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errs() << "Interfere with sub-register ";
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li_->getInterval(*SR).print(errs(), tri_);
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});
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return false; // Not coalescable
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return false; // Not coalescable
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}
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}
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return true;
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return true;
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@ -1212,14 +1235,18 @@ SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
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LiveInterval &RHS = li_->getInterval(DstReg);
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LiveInterval &RHS = li_->getInterval(DstReg);
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if (li_->hasInterval(RealSrcReg) &&
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if (li_->hasInterval(RealSrcReg) &&
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RHS.overlaps(li_->getInterval(RealSrcReg))) {
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RHS.overlaps(li_->getInterval(RealSrcReg))) {
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DOUT << "Interfere with register ";
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DEBUG({
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DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
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errs() << "Interfere with register ";
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li_->getInterval(RealSrcReg).print(errs(), tri_);
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});
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return false; // Not coalescable
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return false; // Not coalescable
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}
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}
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for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
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for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
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if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
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if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
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DOUT << "Interfere with sub-register ";
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DEBUG({
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DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
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errs() << "Interfere with sub-register ";
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li_->getInterval(*SR).print(errs(), tri_);
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});
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return false; // Not coalescable
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return false; // Not coalescable
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}
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}
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return true;
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return true;
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@ -1248,7 +1275,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
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if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
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return false; // Already done.
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return false; // Already done.
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DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
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DEBUG(errs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
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unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
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unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
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bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
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bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
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@ -1268,8 +1295,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
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if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
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// r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
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// r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
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// coalesced to a larger register so the subreg indices cancel out.
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// coalesced to a larger register so the subreg indices cancel out.
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DOUT << "\tSource of insert_subreg is already coalesced "
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DEBUG(errs() << "\tSource of insert_subreg is already coalesced "
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<< "to another register.\n";
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<< "to another register.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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} else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
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} else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
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@ -1278,7 +1305,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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// If they are already joined we continue.
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// If they are already joined we continue.
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if (SrcReg == DstReg) {
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if (SrcReg == DstReg) {
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DOUT << "\tCopy already coalesced.\n";
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DEBUG(errs() << "\tCopy already coalesced.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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@ -1287,17 +1314,17 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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// If they are both physical registers, we cannot join them.
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// If they are both physical registers, we cannot join them.
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if (SrcIsPhys && DstIsPhys) {
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if (SrcIsPhys && DstIsPhys) {
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DOUT << "\tCan not coalesce physregs.\n";
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DEBUG(errs() << "\tCan not coalesce physregs.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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// We only join virtual registers with allocatable physical registers.
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// We only join virtual registers with allocatable physical registers.
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if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
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if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
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DOUT << "\tSrc reg is unallocatable physreg.\n";
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DEBUG(errs() << "\tSrc reg is unallocatable physreg.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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if (DstIsPhys && !allocatableRegs_[DstReg]) {
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if (DstIsPhys && !allocatableRegs_[DstReg]) {
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DOUT << "\tDst reg is unallocatable physreg.\n";
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DEBUG(errs() << "\tDst reg is unallocatable physreg.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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@ -1312,8 +1339,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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assert(DstSubRC && "Illegal subregister index");
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assert(DstSubRC && "Illegal subregister index");
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if (!DstSubRC->contains(SrcSubReg)) {
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if (!DstSubRC->contains(SrcSubReg)) {
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DEBUG(errs() << "\tIncompatible destination regclass: "
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DEBUG(errs() << "\tIncompatible destination regclass: "
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<< tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
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<< tri_->getName(SrcSubReg) << " not in "
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<< ".\n");
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<< DstSubRC->getName() << ".\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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}
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}
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@ -1329,8 +1356,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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assert(SrcSubRC && "Illegal subregister index");
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assert(SrcSubRC && "Illegal subregister index");
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if (!SrcSubRC->contains(DstReg)) {
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if (!SrcSubRC->contains(DstReg)) {
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DEBUG(errs() << "\tIncompatible source regclass: "
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DEBUG(errs() << "\tIncompatible source regclass: "
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<< tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
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<< tri_->getName(DstSubReg) << " not in "
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<< ".\n");
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<< SrcSubRC->getName() << ".\n");
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(void)DstSubReg;
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(void)DstSubReg;
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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@ -1354,7 +1381,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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// r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
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// r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
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// coalesced to a larger register so the subreg indices cancel out.
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// coalesced to a larger register so the subreg indices cancel out.
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if (DstSubIdx != SubIdx) {
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if (DstSubIdx != SubIdx) {
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DOUT << "\t Sub-register indices mismatch.\n";
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DEBUG(errs() << "\t Sub-register indices mismatch.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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} else
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} else
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@ -1367,7 +1394,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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// EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
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// EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
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// coalesced to a larger register so the subreg indices cancel out.
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// coalesced to a larger register so the subreg indices cancel out.
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if (SrcSubIdx != SubIdx) {
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if (SrcSubIdx != SubIdx) {
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DOUT << "\t Sub-register indices mismatch.\n";
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DEBUG(errs() << "\t Sub-register indices mismatch.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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} else
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} else
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@ -1376,8 +1403,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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} else if ((DstIsPhys && isExtSubReg) ||
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} else if ((DstIsPhys && isExtSubReg) ||
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(SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
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(SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
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if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
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if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
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DOUT << "\tSrc of extract_subreg already coalesced with reg"
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DEBUG(errs() << "\tSrc of extract_subreg already coalesced with reg"
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<< " of a super-class.\n";
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<< " of a super-class.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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@ -1400,7 +1427,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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// class as the would be resulting register.
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// class as the would be resulting register.
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SubIdx = 0;
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SubIdx = 0;
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else {
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else {
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DOUT << "\t Sub-register indices mismatch.\n";
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DEBUG(errs() << "\t Sub-register indices mismatch.\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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}
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}
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@ -1412,7 +1439,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
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NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
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}
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}
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if (!NewRC) {
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if (!NewRC) {
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DOUT << "\t Conflicting sub-register indices.\n";
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DEBUG(errs() << "\t Conflicting sub-register indices.\n");
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return false; // Not coalescable
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return false; // Not coalescable
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}
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}
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@ -1485,8 +1512,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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NewRC = getCommonSubClass(SrcRC, DstRC);
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NewRC = getCommonSubClass(SrcRC, DstRC);
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if (!NewRC) {
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if (!NewRC) {
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DEBUG(errs() << "\tDisjoint regclasses: "
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DEBUG(errs() << "\tDisjoint regclasses: "
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<< SrcRC->getName() << ", "
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<< SrcRC->getName() << ", "
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<< DstRC->getName() << ".\n");
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<< DstRC->getName() << ".\n");
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return false; // Not coalescable.
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return false; // Not coalescable.
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}
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}
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if (DstRC->getSize() > SrcRC->getSize())
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if (DstRC->getSize() > SrcRC->getSize())
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@ -1500,7 +1527,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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(isExtSubReg || DstRC->isASubClass()) &&
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(isExtSubReg || DstRC->isASubClass()) &&
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!isWinToJoinCrossClass(LargeReg, SmallReg,
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!isWinToJoinCrossClass(LargeReg, SmallReg,
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allocatableRCRegs_[NewRC].count())) {
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allocatableRCRegs_[NewRC].count())) {
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DOUT << "\tSrc/Dest are different register classes.\n";
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DEBUG(errs() << "\tSrc/Dest are different register classes.\n");
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// Allow the coalescer to try again in case either side gets coalesced to
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// Allow the coalescer to try again in case either side gets coalesced to
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// a physical register that's compatible with the other side. e.g.
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// a physical register that's compatible with the other side. e.g.
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// r1024 = MOV32to32_ r1025
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// r1024 = MOV32to32_ r1025
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@ -1521,9 +1548,11 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
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assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
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"Register mapping is horribly broken!");
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"Register mapping is horribly broken!");
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DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
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DEBUG({
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DOUT << " and "; DstInt.print(DOUT, tri_);
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errs() << "\t\tInspecting "; SrcInt.print(errs(), tri_);
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DOUT << ": ";
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errs() << " and "; DstInt.print(errs(), tri_);
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errs() << ": ";
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});
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// Save a copy of the virtual register live interval. We'll manually
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// Save a copy of the virtual register live interval. We'll manually
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// merge this into the "real" physical register live interval this is
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// merge this into the "real" physical register live interval this is
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@ -1553,7 +1582,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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|||||||
if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
|
if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
|
||||||
mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
|
mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
|
||||||
++numAborts;
|
++numAborts;
|
||||||
DOUT << "\tMay tie down a physical register, abort!\n";
|
DEBUG(errs() << "\tMay tie down a physical register, abort!\n");
|
||||||
Again = true; // May be possible to coalesce later.
|
Again = true; // May be possible to coalesce later.
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
@ -1561,7 +1590,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
|
|||||||
if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
|
if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
|
||||||
mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
|
mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
|
||||||
++numAborts;
|
++numAborts;
|
||||||
DOUT << "\tMay tie down a physical register, abort!\n";
|
DEBUG(errs() << "\tMay tie down a physical register, abort!\n");
|
||||||
Again = true; // May be possible to coalesce later.
|
Again = true; // May be possible to coalesce later.
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
@ -1585,7 +1614,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
|
|||||||
mri_->use_end()) / Length) < Ratio)) {
|
mri_->use_end()) / Length) < Ratio)) {
|
||||||
mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
|
mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
|
||||||
++numAborts;
|
++numAborts;
|
||||||
DOUT << "\tMay tie down a physical register, abort!\n";
|
DEBUG(errs() << "\tMay tie down a physical register, abort!\n");
|
||||||
Again = true; // May be possible to coalesce later.
|
Again = true; // May be possible to coalesce later.
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
@ -1604,7 +1633,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
|
|||||||
// Only coalesce an empty interval (defined by implicit_def) with
|
// Only coalesce an empty interval (defined by implicit_def) with
|
||||||
// another interval which has a valno defined by the CopyMI and the CopyMI
|
// another interval which has a valno defined by the CopyMI and the CopyMI
|
||||||
// is a kill of the implicit def.
|
// is a kill of the implicit def.
|
||||||
DOUT << "Not profitable!\n";
|
DEBUG(errs() << "Not profitable!\n");
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1626,7 +1655,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Otherwise, we are unable to join the intervals.
|
// Otherwise, we are unable to join the intervals.
|
||||||
DOUT << "Interference!\n";
|
DEBUG(errs() << "Interference!\n");
|
||||||
Again = true; // May be possible to coalesce later.
|
Again = true; // May be possible to coalesce later.
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
@ -1749,8 +1778,11 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
|
|||||||
mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
|
mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
|
DEBUG({
|
||||||
DOUT << "\n";
|
errs() << "\n\t\tJoined. Result = ";
|
||||||
|
ResDstInt->print(errs(), tri_);
|
||||||
|
errs() << "\n";
|
||||||
|
});
|
||||||
|
|
||||||
++numJoins;
|
++numJoins;
|
||||||
return true;
|
return true;
|
||||||
@ -2060,8 +2092,10 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
|
|||||||
} else {
|
} else {
|
||||||
for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
|
for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
|
||||||
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
|
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
|
||||||
DOUT << "Interfere with sub-register ";
|
DEBUG({
|
||||||
DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
|
errs() << "Interfere with sub-register ";
|
||||||
|
li_->getInterval(*SR).print(errs(), tri_);
|
||||||
|
});
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2075,8 +2109,10 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
|
|||||||
} else {
|
} else {
|
||||||
for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
|
for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
|
||||||
if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
|
if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
|
||||||
DOUT << "Interfere with sub-register ";
|
DEBUG({
|
||||||
DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
|
errs() << "Interfere with sub-register ";
|
||||||
|
li_->getInterval(*SR).print(errs(), tri_);
|
||||||
|
});
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2402,7 +2438,7 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
|
|||||||
}
|
}
|
||||||
|
|
||||||
void SimpleRegisterCoalescing::joinIntervals() {
|
void SimpleRegisterCoalescing::joinIntervals() {
|
||||||
DOUT << "********** JOINING INTERVALS ***********\n";
|
DEBUG(errs() << "********** JOINING INTERVALS ***********\n");
|
||||||
|
|
||||||
if (NewHeuristic)
|
if (NewHeuristic)
|
||||||
JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
|
JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
|
||||||
@ -2592,8 +2628,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
|
|||||||
loopInfo = &getAnalysis<MachineLoopInfo>();
|
loopInfo = &getAnalysis<MachineLoopInfo>();
|
||||||
|
|
||||||
DEBUG(errs() << "********** SIMPLE REGISTER COALESCING **********\n"
|
DEBUG(errs() << "********** SIMPLE REGISTER COALESCING **********\n"
|
||||||
<< "********** Function: "
|
<< "********** Function: "
|
||||||
<< ((Value*)mf_->getFunction())->getName() << '\n');
|
<< ((Value*)mf_->getFunction())->getName() << '\n');
|
||||||
|
|
||||||
allocatableRegs_ = tri_->getAllocatableSet(fn);
|
allocatableRegs_ = tri_->getAllocatableSet(fn);
|
||||||
for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
|
for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
|
||||||
@ -2605,10 +2641,10 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
|
|||||||
if (EnableJoining) {
|
if (EnableJoining) {
|
||||||
joinIntervals();
|
joinIntervals();
|
||||||
DEBUG({
|
DEBUG({
|
||||||
DOUT << "********** INTERVALS POST JOINING **********\n";
|
errs() << "********** INTERVALS POST JOINING **********\n";
|
||||||
for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
|
for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
|
||||||
I->second->print(DOUT, tri_);
|
I->second->print(errs(), tri_);
|
||||||
DOUT << "\n";
|
errs() << "\n";
|
||||||
}
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user