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Don't insert 128-bit UNDEF into 256-bit vectors. Just keep the 256-bit vector. Original patch by Elena Demikhovsky. Tweaked by me to allow possibility of covering more cases.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158792 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-06-20 05:39:26 +00:00
parent 37aa33bc11
commit 703c38bf58
3 changed files with 15 additions and 4 deletions
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9
lib/Target/X86/X86ISelLowering.cpp
View File

@ -99,6 +99,10 @@ static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
unsigned IdxVal, SelectionDAG &DAG,
DebugLoc dl) {
// Inserting UNDEF is Result
if (Vec.getOpcode() == ISD::UNDEF)
return Result;
EVT VT = Vec.getValueType();
assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
@ -114,9 +118,8 @@ static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
* ElemsPerChunk);
SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
VecIdx);
return Result;
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
VecIdx);
}
/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128

2
test/CodeGen/X86/avx-shuffle-x86_32.ll
View File

@ -4,5 +4,5 @@ define <4 x i64> @test1(<4 x i64> %a) nounwind {
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i64>%b
; CHECK: test1:
; CHECK: vinsertf128
; CHECK-NOT: vinsertf128
}

8
test/CodeGen/X86/avx-shuffle.ll
View File

@ -219,3 +219,11 @@ define <16 x i16> @narrow(<16 x i16> %a) nounwind alwaysinline {
%t = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 1, i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 8, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
ret <16 x i16> %t
}
;CHECK: test17
;CHECK-NOT: vinsertf128
;CHECK: ret
define <8 x float> @test17(<4 x float> %y) {
%x = shufflevector <4 x float> %y, <4 x float> undef, <8 x i32> <i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %x
}