6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-17 21:35:07 +00:00
Code Issues Projects Releases Wiki Activity

Teach the SelectionDAG how to transform select_cc eq, X, 0, 1, 0 into

Browse Source 
either seteq X, 0 or srl (ctlz X), size(X-1), depending on what's legal
for the target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-08-23 05:41:12 +00:00
parent b942a3dd5f
commit 7042f15bde
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -853,6 +853,23 @@ SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2,
}
}
// Check to see if this is the equivalent of seteq X, 0.
// select_cc seteq X, 0, 1, 0 -> setcc X, 0, seteq -> srl (ctlz X), size(X)-1
if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() &&
N3C && (N3C->getValue() == 1)) {
MVT::ValueType XType = N1.getValueType();
if (TLI.getOperationAction(ISD::SETCC, TLI.getSetCCResultTy()) ==
TargetLowering::Legal) {
return getSetCC(TLI.getSetCCResultTy(), N1, N2, ISD::SETEQ);
}
if (TLI.getOperationAction(ISD::CTLZ, XType) == TargetLowering::Legal) {
SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1);
return getNode(ISD::SRL, XType, Ctlz,
getConstant(MVT::getSizeInBits(XType)-1,
TLI.getShiftAmountTy()));
}
}
// Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&