mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
f475a55bd4
commit
705f2431a0
@ -2845,16 +2845,12 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPD:
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case X86ISD::VUNPCKLPSY:
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case X86ISD::VUNPCKLPDY:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::PUNPCKLQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHDQ:
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@ -2926,16 +2922,12 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPD:
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case X86ISD::VUNPCKLPSY:
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case X86ISD::VUNPCKLPDY:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::PUNPCKLQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHDQ:
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@ -4651,8 +4643,6 @@ static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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break;
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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DecodeUNPCKHPMask(VT, ShuffleMask);
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break;
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case X86ISD::PUNPCKLBW:
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@ -4663,8 +4653,6 @@ static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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break;
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPD:
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case X86ISD::VUNPCKLPSY:
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case X86ISD::VUNPCKLPDY:
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DecodeUNPCKLPMask(VT, ShuffleMask);
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break;
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case X86ISD::MOVHLPS:
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@ -6582,16 +6570,16 @@ static inline unsigned getUNPCKLOpcode(EVT VT, bool HasAVX2) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v4i32: return X86ISD::PUNPCKLDQ;
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case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
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case MVT::v4f32: return X86ISD::UNPCKLPS;
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case MVT::v2f64: return X86ISD::UNPCKLPD;
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case MVT::v8i32:
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if (HasAVX2) return X86ISD::PUNPCKLDQ;
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// else use fp unit for int unpack.
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case MVT::v8f32: return X86ISD::VUNPCKLPSY;
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case MVT::v8f32:
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case MVT::v4f32: return X86ISD::UNPCKLPS;
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case MVT::v4i64:
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if (HasAVX2) return X86ISD::PUNPCKLQDQ;
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// else use fp unit for int unpack.
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case MVT::v4f64: return X86ISD::VUNPCKLPDY;
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case MVT::v4f64:
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case MVT::v2f64: return X86ISD::UNPCKLPD;
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case MVT::v32i8:
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case MVT::v16i8: return X86ISD::PUNPCKLBW;
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case MVT::v16i16:
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@ -6606,16 +6594,16 @@ static inline unsigned getUNPCKHOpcode(EVT VT, bool HasAVX2) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v4i32: return X86ISD::PUNPCKHDQ;
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case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
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case MVT::v4f32: return X86ISD::UNPCKHPS;
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case MVT::v2f64: return X86ISD::UNPCKHPD;
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case MVT::v8i32:
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if (HasAVX2) return X86ISD::PUNPCKHDQ;
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// else use fp unit for int unpack.
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case MVT::v8f32: return X86ISD::VUNPCKHPSY;
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case MVT::v8f32:
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case MVT::v4f32: return X86ISD::UNPCKHPS;
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case MVT::v4i64:
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if (HasAVX2) return X86ISD::PUNPCKHQDQ;
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// else use fp unit for int unpack.
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case MVT::v4f64: return X86ISD::VUNPCKHPDY;
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case MVT::v4f64:
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case MVT::v2f64: return X86ISD::UNPCKHPD;
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case MVT::v32i8:
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case MVT::v16i8: return X86ISD::PUNPCKHBW;
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case MVT::v16i16:
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@ -11280,8 +11268,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MOVSS: return "X86ISD::MOVSS";
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case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
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case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
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case X86ISD::VUNPCKLPSY: return "X86ISD::VUNPCKLPSY";
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case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
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case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
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case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
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case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
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@ -14877,16 +14863,12 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::PUNPCKHQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::PUNPCKLQDQ:
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPD:
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case X86ISD::VUNPCKLPSY:
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case X86ISD::VUNPCKLPDY:
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case X86ISD::MOVHLPS:
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case X86ISD::MOVLHPS:
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case X86ISD::PSHUFD:
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@ -275,12 +275,8 @@ namespace llvm {
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MOVSS,
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UNPCKLPS,
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UNPCKLPD,
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VUNPCKLPSY,
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VUNPCKLPDY,
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UNPCKHPS,
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UNPCKHPD,
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VUNPCKHPSY,
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VUNPCKHPDY,
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PUNPCKLBW,
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PUNPCKLWD,
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PUNPCKLDQ,
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@ -132,13 +132,9 @@ def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
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def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
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def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
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def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>;
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def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>;
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def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
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def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
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def X86Unpckhpsy : SDNode<"X86ISD::VUNPCKHPSY", SDTShuff2Op>;
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def X86Unpckhpdy : SDNode<"X86ISD::VUNPCKHPDY", SDTShuff2Op>;
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def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>;
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def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>;
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@ -2472,21 +2472,21 @@ let Predicates = [HasAVX] in {
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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(VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
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def : Pat<(v8f32 (X86Unpcklps VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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def : Pat<(v8f32 (X86Unpcklps VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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def : Pat<(v8i32 (X86Unpcklps VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
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def : Pat<(v8i32 (X86Unpcklps VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
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def : Pat<(v8f32 (X86Unpckhps VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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def : Pat<(v8f32 (X86Unpckhps VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
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def : Pat<(v8i32 (X86Unpckhps VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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def : Pat<(v8i32 (X86Unpckhps VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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@ -2498,21 +2498,21 @@ let Predicates = [HasAVX] in {
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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(VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
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def : Pat<(v4f64 (X86Unpcklpd VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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def : Pat<(v4f64 (X86Unpcklpd VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
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def : Pat<(v4i64 (X86Unpcklpd VR256:$src1, (memopv4i64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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def : Pat<(v4i64 (X86Unpcklpd VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
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def : Pat<(v4f64 (X86Unpckhpd VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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def : Pat<(v4f64 (X86Unpckhpd VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
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def : Pat<(v4i64 (X86Unpckhpd VR256:$src1, (memopv4i64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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def : Pat<(v4i64 (X86Unpckhpd VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
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@ -67,6 +67,15 @@ entry:
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ret <8 x i32> %shuffle.i
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}
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; CHECK: vunpckhps (%
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define <8 x i32> @unpackhips2(<8 x i32>* %src1, <8 x i32>* %src2) nounwind uwtable readnone ssp {
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entry:
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%a = load <8 x i32>* %src1
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%b = load <8 x i32>* %src2
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%shuffle.i = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
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ret <8 x i32> %shuffle.i
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}
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; CHECK: vunpckhpd
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define <4 x i64> @unpackhipd1(<4 x i64> %src1, <4 x i64> %src2) nounwind uwtable readnone ssp {
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entry:
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@ -74,6 +83,15 @@ entry:
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ret <4 x i64> %shuffle.i
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}
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; CHECK: vunpckhpd (%
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define <4 x i64> @unpackhipd2(<4 x i64>* %src1, <4 x i64>* %src2) nounwind uwtable readnone ssp {
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entry:
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%a = load <4 x i64>* %src1
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%b = load <4 x i64>* %src2
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%shuffle.i = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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ret <4 x i64> %shuffle.i
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}
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; CHECK: vunpcklps
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define <8 x i32> @unpacklops1(<8 x i32> %src1, <8 x i32> %src2) nounwind uwtable readnone ssp {
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entry:
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@ -81,9 +99,27 @@ entry:
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ret <8 x i32> %shuffle.i
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}
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; CHECK: vunpcklps (%
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define <8 x i32> @unpacklops2(<8 x i32>* %src1, <8 x i32>* %src2) nounwind uwtable readnone ssp {
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entry:
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%a = load <8 x i32>* %src1
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%b = load <8 x i32>* %src2
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%shuffle.i = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
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ret <8 x i32> %shuffle.i
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}
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; CHECK: vunpcklpd
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define <4 x i64> @unpacklopd1(<4 x i64> %src1, <4 x i64> %src2) nounwind uwtable readnone ssp {
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entry:
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%shuffle.i = shufflevector <4 x i64> %src1, <4 x i64> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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ret <4 x i64> %shuffle.i
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}
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; CHECK: vunpcklpd (%
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define <4 x i64> @unpacklopd2(<4 x i64>* %src1, <4 x i64>* %src2) nounwind uwtable readnone ssp {
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entry:
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%a = load <4 x i64>* %src1
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%b = load <4 x i64>* %src2
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%shuffle.i = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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ret <4 x i64> %shuffle.i
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}
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