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update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22807 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-16 21:56:37 +00:00
parent d5d0f9bd20
commit 707ebc5dd6
3 changed files with 49 additions and 47 deletions
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21
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -283,7 +283,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::f64:
case MVT::f32:
args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
argt = DAG.getCopyFromReg(args_float[count], VT, DAG.getRoot());
argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
break;
case MVT::i1:
case MVT::i8:
@ -292,7 +292,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::i64:
args_int[count] = AddLiveIn(MF, args_int[count],
getRegClassFor(MVT::i64));
argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT);
if (VT != MVT::i64)
argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
break;
@ -319,7 +319,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
for (int i = 0; i < 6; ++i) {
if (args_int[i] < 1024)
args_int[i] = AddLiveIn(MF,args_int[i], getRegClassFor(MVT::i64));
SDOperand argt = DAG.getCopyFromReg(args_int[i], MVT::i64, DAG.getRoot());
SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
@ -328,7 +328,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
if (args_float[i] < 1024)
args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64));
argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot());
argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
@ -1634,7 +1634,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
SDOperand Chain = N.getOperand(0);
Select(Chain);
unsigned r = cast<RegSDNode>(Node)->getReg();
unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
@ -2199,7 +2199,8 @@ void AlphaISel::Select(SDOperand N) {
case ISD::ImplicitDef:
++count_ins;
Select(N.getOperand(0));
BuildMI(BB, Alpha::IDEF, 0, cast<RegSDNode>(N)->getReg());
BuildMI(BB, Alpha::IDEF, 0,
cast<RegisterSDNode>(N.getOperand(1))->getReg());
return;
case ISD::EntryToken: return; // Noop
@ -2216,12 +2217,12 @@ void AlphaISel::Select(SDOperand N) {
case ISD::CopyToReg:
++count_outs;
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = cast<RegSDNode>(N)->getReg();
Tmp1 = SelectExpr(N.getOperand(2));
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
if (N.getOperand(1).getValueType() == MVT::f64 ||
N.getOperand(1).getValueType() == MVT::f32)
if (N.getOperand(2).getValueType() == MVT::f64 ||
N.getOperand(2).getValueType() == MVT::f32)
BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
else
BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);

21
lib/Target/IA64/IA64ISelPattern.cpp
View File

@ -201,8 +201,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// FP args go into f8..f15 as needed: (hence the ++)
argPreg[count] = args_FP[used_FPArgs++];
argOpc[count] = IA64::FMOV;
argt = newroot = DAG.getCopyFromReg(argVreg[count],
getValueType(I->getType()), DAG.getRoot());
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
getValueType(I->getType()));
break;
case MVT::i1: // NOTE: as far as C abi stuff goes,
// bools are just boring old ints
@ -217,7 +217,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
argPreg[count] = args_int[count];
argOpc[count] = IA64::MOV;
argt = newroot =
DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
if ( getValueType(I->getType()) != MVT::i64)
argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
newroot);
@ -919,7 +919,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (Node->getOpcode() == ISD::CopyFromReg)
// Just use the specified register as our input.
return dyn_cast<RegSDNode>(Node)->getReg();
return cast<RegisterSDNode>(Node->getOperand(1))->getReg();
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
@ -2026,7 +2026,7 @@ pC = pA OR pB
SDOperand Chain = N.getOperand(0);
Select(Chain);
unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if(N.getValueType() == MVT::i1) // if a bool, we use pseudocode
BuildMI(BB, IA64::PCMPEQUNC, 3, Result)
@ -2209,17 +2209,19 @@ void ISel::Select(SDOperand N) {
case ISD::CopyToReg: {
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = cast<RegSDNode>(N)->getReg();
Tmp1 = SelectExpr(N.getOperand(2));
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
if(N.getValueType() == MVT::i1) // if a bool, we use pseudocode
// if a bool, we use pseudocode
if (N.getOperand(2).getValueType() == MVT::i1)
BuildMI(BB, IA64::PCMPEQUNC, 3, Tmp2)
.addReg(IA64::r0).addReg(IA64::r0).addReg(Tmp1);
// (Tmp1) Tmp2 = cmp.eq.unc(r0,r0)
else
BuildMI(BB, IA64::MOV, 1, Tmp2).addReg(Tmp1);
// XXX is this the right way 'round? ;)
// FIXME: WHAT ABOUT FLOATING POINT?
}
return;
}
@ -2288,7 +2290,8 @@ void ISel::Select(SDOperand N) {
case ISD::ImplicitDef: {
Select(N.getOperand(0));
BuildMI(BB, IA64::IDEF, 0, cast<RegSDNode>(N)->getReg());
BuildMI(BB, IA64::IDEF, 0,
cast<RegisterSDNode>(N.getOperand(1))->getReg());
return;
}

54
lib/Target/X86/X86ISelPattern.cpp
View File

@ -429,8 +429,8 @@ X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
// Arguments go on the stack in reverse order, as specified by the ABI.
unsigned ArgOffset = 0;
SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
DAG.getEntryNode());
SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
X86::ESP, MVT::i32);
std::vector<SDOperand> Stores;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
@ -627,7 +627,7 @@ X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
if (!I->use_empty()) {
unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
X86::R8RegisterClass);
ArgValue = DAG.getCopyFromReg(VReg, MVT::i8, DAG.getRoot());
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
DAG.setRoot(ArgValue.getValue(1));
}
++NumIntRegs;
@ -641,7 +641,7 @@ X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
if (!I->use_empty()) {
unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
X86::R16RegisterClass);
ArgValue = DAG.getCopyFromReg(VReg, MVT::i16, DAG.getRoot());
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
DAG.setRoot(ArgValue.getValue(1));
}
++NumIntRegs;
@ -654,7 +654,7 @@ X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
if (!I->use_empty()) {
unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
X86::R32RegisterClass);
ArgValue = DAG.getCopyFromReg(VReg, MVT::i32, DAG.getRoot());
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
DAG.setRoot(ArgValue.getValue(1));
}
++NumIntRegs;
@ -668,8 +668,8 @@ X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
SDOperand Low=DAG.getCopyFromReg(BotReg, MVT::i32, DAG.getRoot());
SDOperand Hi =DAG.getCopyFromReg(TopReg, MVT::i32, Low.getValue(1));
SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
DAG.setRoot(Hi.getValue(1));
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
@ -679,7 +679,7 @@ X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
} else if (NumIntRegs == 1) {
if (!I->use_empty()) {
unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
SDOperand Low = DAG.getCopyFromReg(BotReg, MVT::i32, DAG.getRoot());
SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
DAG.setRoot(Low.getValue(1));
// Load the high part from memory.
@ -809,8 +809,8 @@ X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
// Arguments go on the stack in reverse order, as specified by the ABI.
unsigned ArgOffset = 0;
SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
DAG.getEntryNode());
SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
X86::ESP, MVT::i32);
NumIntRegs = 0;
std::vector<SDOperand> Stores;
std::vector<SDOperand> RegValuesToPass;
@ -2249,11 +2249,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
SDOperand Op0, Op1;
if (Node->getOpcode() == ISD::CopyFromReg) {
if (MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) ||
cast<RegSDNode>(Node)->getReg() == X86::ESP) {
// Just use the specified register as our input.
return cast<RegSDNode>(Node)->getReg();
}
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
// Just use the specified register as our input if we can.
if (MRegisterInfo::isVirtualRegister(Reg) || Reg == X86::ESP)
return Reg;
}
unsigned &Reg = ExprMap[N];
@ -2310,20 +2309,18 @@ unsigned ISel::SelectExpr(SDOperand N) {
Reg = Result = ExprMap[N.getValue(0)] =
MakeReg(N.getValue(0).getValueType());
}
Tmp1 = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
switch (Node->getValueType(0)) {
default: assert(0 && "Cannot CopyFromReg this!");
case MVT::i1:
case MVT::i8:
BuildMI(BB, X86::MOV8rr, 1,
Result).addReg(cast<RegSDNode>(Node)->getReg());
BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
return Result;
case MVT::i16:
BuildMI(BB, X86::MOV16rr, 1,
Result).addReg(cast<RegSDNode>(Node)->getReg());
BuildMI(BB, X86::MOV16rr, 1, Result).addReg(Tmp1);
return Result;
case MVT::i32:
BuildMI(BB, X86::MOV32rr, 1,
Result).addReg(cast<RegSDNode>(Node)->getReg());
BuildMI(BB, X86::MOV32rr, 1, Result).addReg(Tmp1);
return Result;
}
@ -4012,13 +4009,14 @@ static SDOperand GetAdjustedArgumentStores(SDOperand Chain, int Offset,
if (OrigDest.getOpcode() == ISD::CopyFromReg) {
OrigOffset = 0;
assert(cast<RegSDNode>(OrigDest)->getReg() == X86::ESP);
assert(cast<RegisterSDNode>(OrigDest.getOperand(1))->getReg() == X86::ESP);
} else {
// We expect only (ESP+C)
assert(OrigDest.getOpcode() == ISD::ADD &&
isa<ConstantSDNode>(OrigDest.getOperand(1)) &&
OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg &&
cast<RegSDNode>(OrigDest.getOperand(0))->getReg() == X86::ESP);
cast<RegisterSDNode>(OrigDest.getOperand(0).getOperand(1))->getReg()
== X86::ESP);
OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue();
}
@ -4181,17 +4179,17 @@ void ISel::Select(SDOperand N) {
}
return;
case ISD::CopyToReg:
if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp1 = SelectExpr(N.getOperand(2));
} else {
Tmp1 = SelectExpr(N.getOperand(1));
Tmp1 = SelectExpr(N.getOperand(2));
Select(N.getOperand(0));
}
Tmp2 = cast<RegSDNode>(N)->getReg();
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
switch (N.getOperand(1).getValueType()) {
switch (N.getOperand(2).getValueType()) {
default: assert(0 && "Invalid type for operation!");
case MVT::i1:
case MVT::i8: Opc = X86::MOV8rr; break;