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ARM64: implement cunning optimisation from AArch64
A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3026,6 +3026,59 @@ def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
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def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
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(DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
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// If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
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// instruction even if the types don't match: we just have to remap the lane
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// carefully. N.b. this trick only applies to truncations.
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def VecIndex_x2 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
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}]>;
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def VecIndex_x4 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
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}]>;
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def VecIndex_x8 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
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}]>;
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multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
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ValueType Src128VT, ValueType ScalVT,
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Instruction DUP, SDNodeXForm IdxXFORM> {
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def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
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imm:$idx)))),
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(DUP V128:$Rn, (IdxXFORM imm:$idx))>;
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def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
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imm:$idx)))),
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(DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
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}
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defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
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defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
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defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
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defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
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defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
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defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
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multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
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SDNodeXForm IdxXFORM> {
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def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
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imm:$idx))))),
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(DUP V128:$Rn, (IdxXFORM imm:$idx))>;
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def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
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imm:$idx))))),
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(DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
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}
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defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
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defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
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defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
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defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
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defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
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defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
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// SMOV and UMOV definitions, with some extra patterns for convenience
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defm SMOV : SMov;
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defm UMOV : UMov;
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@ -297,10 +297,11 @@ define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
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; the scalar corresponding to the vector type is illegal (e.g. a <4 x i16>
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; BUILD_VECTOR will have an i32 as its source). In that case, the operation is
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; not a simple "dup vD.4h, vN.h[idx]" after all, and we crashed.
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;
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; *However*, it is a dup vD.4h, vN.h[2*idx].
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define <4 x i16> @test_build_illegal(<4 x i32> %in) {
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; CHECK-LABEL: test_build_illegal:
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; CHECK: umov.s [[WTMP:w[0-9]+]], v0[3]
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; CHECK: dup.4h v0, [[WTMP]]
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; CHECK: dup.4h v0, v0[6]
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%val = extractelement <4 x i32> %in, i32 3
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%smallval = trunc i32 %val to i16
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%vec = insertelement <4x i16> undef, i16 %smallval, i32 3
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