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Support for ADDC/SUBC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43119 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -145,6 +145,7 @@ private:
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void ExpandResult_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SELECT_CC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_MUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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@ -547,8 +548,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
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N->getSrcValue(), N->getSrcValueOffset(),
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N->getLoadedVT(), N->isVolatile(),
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N->getAlignment());
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// Legalized the chain result, switching anything that used the old chain to
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceLegalValueWith(SDOperand(N, 1), Res.getValue(1));
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return Res;
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@ -610,6 +611,8 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
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case ISD::XOR: ExpandResult_Logical(N, Lo, Hi); break;
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case ISD::ADD:
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case ISD::SUB: ExpandResult_ADDSUB(N, Lo, Hi); break;
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case ISD::ADDC:
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case ISD::SUBC: ExpandResult_ADDSUBC(N, Lo, Hi); break;
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case ISD::SELECT: ExpandResult_SELECT(N, Lo, Hi); break;
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case ISD::SELECT_CC: ExpandResult_SELECT_CC(N, Lo, Hi); break;
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case ISD::MUL: ExpandResult_MUL(N, Lo, Hi); break;
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@ -759,7 +762,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
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}
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}
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// Legalized the chain result, switching anything that used the old chain to
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceLegalValueWith(SDOperand(N, 1), Ch);
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}
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@ -823,11 +826,9 @@ void DAGTypeLegalizer::ExpandResult_ADDSUB(SDNode *N,
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GetExpandedOp(N->getOperand(0), LHSL, LHSH);
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GetExpandedOp(N->getOperand(1), RHSL, RHSH);
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SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
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SDOperand LoOps[2], HiOps[3];
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LoOps[0] = LHSL;
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LoOps[1] = RHSL;
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HiOps[0] = LHSH;
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HiOps[1] = RHSH;
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SDOperand LoOps[2] = { LHSL, RHSL };
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SDOperand HiOps[3] = { LHSH, RHSH };
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if (N->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
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HiOps[2] = Lo.getValue(1);
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@ -839,6 +840,30 @@ void DAGTypeLegalizer::ExpandResult_ADDSUB(SDNode *N,
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}
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}
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void DAGTypeLegalizer::ExpandResult_ADDSUBC(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// Expand the subcomponents.
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SDOperand LHSL, LHSH, RHSL, RHSH;
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GetExpandedOp(N->getOperand(0), LHSL, LHSH);
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GetExpandedOp(N->getOperand(1), RHSL, RHSH);
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SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
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SDOperand LoOps[2] = { LHSL, RHSL };
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SDOperand HiOps[3] = { LHSH, RHSH };
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if (N->getOpcode() == ISD::ADDC) {
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Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
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HiOps[2] = Lo.getValue(1);
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Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
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} else {
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Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
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HiOps[2] = Lo.getValue(1);
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Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
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}
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// Legalized the flag result - switch anything that used the old flag to
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// use the new one.
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ReplaceLegalValueWith(SDOperand(N, 1), Hi.getValue(1));
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}
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void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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