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[Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241600 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2015-07-07 16:02:11 +00:00
parent 9fb4897162
commit 70bb40bd17
2 changed files with 8 additions and 12 deletions
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11
lib/Target/Hexagon/BitTracker.cpp
View File

@ -527,8 +527,7 @@ BT::RegisterCell BT::MachineEvaluator::eMLU(const RegisterCell &A1,
BT::RegisterCell BT::MachineEvaluator::eASL(const RegisterCell &A1,
uint16_t Sh) const {
uint16_t W = A1.width();
assert(Sh <= W);
assert(Sh <= A1.width());
RegisterCell Res = RegisterCell::ref(A1);
Res.rol(Sh);
Res.fill(0, Sh, BitValue::Zero);
@ -644,8 +643,7 @@ BT::RegisterCell BT::MachineEvaluator::eNOT(const RegisterCell &A1) const {
BT::RegisterCell BT::MachineEvaluator::eSET(const RegisterCell &A1,
uint16_t BitN) const {
uint16_t W = A1.width();
assert(BitN < W);
assert(BitN < A1.width());
RegisterCell Res = RegisterCell::ref(A1);
Res[BitN] = BitValue::One;
return Res;
@ -654,8 +652,7 @@ BT::RegisterCell BT::MachineEvaluator::eSET(const RegisterCell &A1,
BT::RegisterCell BT::MachineEvaluator::eCLR(const RegisterCell &A1,
uint16_t BitN) const {
uint16_t W = A1.width();
assert(BitN < W);
assert(BitN < A1.width());
RegisterCell Res = RegisterCell::ref(A1);
Res[BitN] = BitValue::Zero;
return Res;
@ -722,6 +719,7 @@ BT::RegisterCell BT::MachineEvaluator::eXTR(const RegisterCell &A1,
BT::RegisterCell BT::MachineEvaluator::eINS(const RegisterCell &A1,
const RegisterCell &A2, uint16_t AtN) const {
uint16_t W1 = A1.width(), W2 = A2.width();
(void)W1;
assert(AtN < W1 && AtN+W2 <= W1);
// Copy bits from A1, insert A2 at position AtN.
RegisterCell Res = RegisterCell::ref(A1);
@ -1017,6 +1015,7 @@ void BT::subst(RegisterRef OldRR, RegisterRef NewRR) {
BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub);
uint16_t OMB = OM.first(), OME = OM.last();
uint16_t NMB = NM.first(), NME = NM.last();
(void)NME;
assert((OME-OMB == NME-NMB) &&
"Substituting registers of different lengths");
for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) {

9
lib/Target/Hexagon/HexagonBitTracker.cpp
View File

@ -195,15 +195,13 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
return eIMM(Op.getImm(), W);
if (!Op.isReg())
return RegisterCell::self(0, W);
uint16_t w = getRegBitWidth(Reg[N]);
assert(w == W && "Register width mismatch");
assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
return rc(N);
};
// Extract RW low bits of the cell.
auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
-> BT::RegisterCell {
uint16_t W = RC.width();
assert(RW <= W);
assert(RW <= RC.width());
return eXTR(RC, 0, RW);
};
// Extract RW high bits of the cell.
@ -216,8 +214,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
// Extract N-th halfword (counting from the least significant position).
auto half = [this] (const BT::RegisterCell &RC, unsigned N)
-> BT::RegisterCell {
uint16_t W = RC.width();
assert(N*16+16 <= W);
assert(N*16+16 <= RC.width());
return eXTR(RC, N*16, N*16+16);
};
// Shuffle bits (pick even/odd from cells and merge into result).